Investigation of negative bias temperature instability dependence on fin width of silicon-on-insulator-fin-based field effect transistors
The fin width dependence of negative bias temperature instability (NBTI) of double-gate, fin-based p-type Field Effect Transistors (FinFETs) fabricated on silicon-on-insulator (SOI) wafers was investigated. The NBTI degradation increased as the fin width narrowed. To investigate this phenomenon, simulations of pre-stress conditions were employed to determine any differences in gate oxide field, fin band bending, and electric field profile as a function of the fin width. The simulation results were similar at a given gate stress bias, regardless of the fin width, although the threshold voltage was found to increase with decreasing fin width. Thus, the NBTI fin width dependence could not be explained from the pre-stress conditions. Different physics-based degradation models were evaluated using specific fin-based device structures with different biasing schemes to ascertain an appropriate model that best explains the measured NBTI dependence. A plausible cause is an accumulation of electrons that tunnel from the gate during stress into the floating SOI fin body. As the fin narrows, the sidewall device channel moves in closer proximity to the stored electrons, thereby inducing more band bending at the fin/dielectric interface, resulting in a higher electric field and hole concentration in this region during stress, which leads to more degradation. The data obtained in this work provide direct experimental proof of the effect of electron accumulation on the threshold voltage stability in FinFETs.