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At least 199 records · Page 11

High density pixel array and laser micro-milling method for fabricating array

A pixel array device is fabricated by a laser micro-milling method under strict process control conditions. The device has an array of pixels bonded together with an adhesive filling the grooves between adjacent pixels. The array is fabricated by moving a substrate relative to a laser beam of predetermined intensity at a controlled, constant velocity along a predetermined path defining a set of grooves between adjacent pixels so that a predetermined laser flux per unit area is applied to the material, and repeating the movement for a plurality of passes of the laser beam until the grooves are ablated to a desired depth. The substrate is of an ultrasonic transducer material in one example for fabrication of a 2D ultrasonic phase array transducer. A substrate of phosphor material is used to fabricate an X-ray focal plane array detector.

Wiener-Avnear, Eliezer↗

Mapping Electrical Crosstalk in Pixelated Sensor Arrays

The effects of inter pixel capacitance in a pixilated array may be measured by first resetting all pixels in the array to a first voltage, where a first image is read out, followed by resetting only a subset of pixels in the array to a second voltage, where a second image is read out, where the difference in the first and second images provide information about the inter pixel capacitance. Other embodiments are described and claimed.

Seshadri, Suresh↗

Mapping Electrical Crosstalk in Pixelated Sensor Arrays

The effects of inter pixel capacitance in a pixilated array may be measured by first resetting all pixels in the array to a first voltage, where a first image is read out, followed by resetting only a subset of pixels in the array to a second voltage, where a second image is read out, where the difference in the first and second images provide information about the inter pixel capacitance. Other embodiments are described and claimed.

Seshadri, Suresh↗

Design and Optimization of Multi-Pixel Transition-Edge Sensors for X-Ray Astronomy Applications

Multi-pixel transition-edge sensors (TESs), commonly referred to as 'hydras', are a type of position sensitive micro-calorimeter that enables very large format arrays to be designed without commensurate increase in the number of readout channels and associated wiring. In the hydra design, a single TES is coupled to discrete absorbers via varied thermal links. The links act as low pass thermal filters that are tuned to give a different characteristic pulse shape for x-ray photons absorbed in each of the hydra sub pixels. In this contribution we report on the experimental results from hydras consisting of up to 20 pixels per TES. We discuss the design trade-offs between energy resolution, position discrimination and number of pixels and investigate future design optimizations specifically targeted at meeting the readout technology considered for Lynx.

Smith, Stephen J.↗

Pixel-Level Calibration in the Kepler Science Operations Center Pipeline

We present an overview of the pixel-level calibration of flight data from the Kepler Mission performed within the Kepler Science Operations Center Science Processing Pipeline. This article describes the calibration (CAL) module, which operates on original spacecraft data to remove instrument effects and other artifacts that pollute the data. Traditional CCD data reduction is performed (removal of instrument/detector effects such as bias and dark current), in addition to pixel-level calibration (correcting for cosmic rays and variations in pixel sensitivity), Kepler-specific corrections (removing smear signals which result from the lack of a shutter on the photometer and correcting for distortions induced by the readout electronics), and additional operations that are needed due to the complexity and large volume of flight data. CAL operates on long (~30 min) and short (~1 min) sampled data, as well as full-frame images, and produces calibrated pixel flux time series, uncertainties, and other metrics that are used in subsequent Pipeline modules. The raw and calibrated data are also archived in the Multi-mission Archive at Space Telescope at the Space Telescope Science Institute for use by the astronomical community.

Calibration↗

Compact 1.9 THz Multi-Pixel Local Oscillator Chain

Single-pixel heterodyne receivers are severely limited in their capability to map large areas on the sky. We report on the development of THz multi-pixel local oscillator sources that ought to enable THz array receivers of the future. We demonstrate a prototype 16-pixel chain at 1.9 THz. Output power in excess of >10 microwatts has been demonstrated per pixel from this compact chain.

Lin, Robert↗

Towards an improved understanding of the influence of subpixel vegetation structure on pixel-level spectra: a simulation approach

The planned NASA Hyperspectral Infrared Imager (HyspIRI) mission, equipped with an imaging spectrometer that has the capability of monitoring ecosystems globally, will provide an unprecedented opportunity to address scientific challenges related to ecosystem function and change. However, uncertainty remains around the impact of subpixel vegetation structure, in combination with the point spread function, on pixel-level imaging spectroscopy data. We estimated structural parameters, e.g., leaf area index (LAI), canopy cover, and tree location, from HyspIRI spectral data, with the goal of assessing how subpixel variation in these parameters impact pixel-level imaging spectroscopy data. The fine-scale variability of real vegetation structure makes this a challenging endeavor. Therefore, we utilized a simulation-based approach to counter the time-consuming and often destructive sampling needs of vegetation structural analysis and to simultaneously generate synthetic HyspIRI data pre-launch. Three virtual scenes were constructed, corresponding to the actual vegetation structure in the National Ecological Observatory Network’s (NEON) Pacific Southwest Domain (Fresno, CA). These included an oak savanna, a dense coniferous forest, and a conifer-manzanita-mixed forest. Simulated spectroscopy data for these scenes were then generated using the Digital Imaging and Remote Sensing Image Generation (DIRSIG) model. Simulations first were used to verify the physical model, virtual scene geometrical information, and simulation parameters. This was followed by simulations of HyspIRI data, where within-pixel structural variability was introduced, e.g., by iteratively changing per-pixel canopy cover and tree placement, tree clustering, leaf area index (LAI), etc., between simulation runs for the virtual scenes. Finally, narrow-band vegetation indices (VIs) were extracted from the data in an attempt to describe the variability of the subpixel structural parameters; this was done in order to assess VI robustness to changes in structural “levels”, as well as placement of trees/canopies within the instrument’s instantaneous field-of-view (IFOV). Our ultimate goal is not only to better understand how such subpixel variability influence imaging spectroscopy outputs, but also to better estimate vegetation structural parameters using spectra. We constructed regression models for LAI (R2 = 0.92) and canopy cover (R2 = 0.97) with narrow-band VIs via this simulation approach. Our models ultimately are intended to improve the HyspIRI mission’s ability to monitor global vegetation structure.

Van Aardt, Jan↗

A Cryogenic Readout IC with 100 KSPS in-Pixel ADC for Skipper CCD-in-CMOS Sensors

The Skipper CCD-in-CMOS Parallel Read-Out Circuit (SPROCKET) is a mixed-signal front-end design for the readout of Skipper CCD-in-CMOS image sensors. SPROCKET is fabricated in a 65 nm CMOS process and each pixel occupies a 50$\mu$m $\times$ 50$\mu$m footprint. SPROCKET is intended to be heterogeneously integrated with a Skipper-in-CMOS sensor array, such that one readout pixel is connected to a multiplexed array of nine Skipper-in-CMOS pixels to enable massively parallel readout. The front-end includes a variable gain preamplifier, a correlated double sampling circuit, and a 10-bit serial successive approximation register (SAR) ADC. The circuit achieves a sample rate of 100 ksps with 0.48 $\mathrm{e^-_{rms}}$ equivalent noise at the input to the ADC. SPROCKET achieves a maximum dynamic range of 9,000 $e^-$ at the lowest gain setting (or 900 $e^-$ at the lowest noise setting). The circuit operates at 100 Kelvin with a power consumption of 40 $\mu W$ per pixel. A SPROCKET test chip was submitted in September 2022, and test results will be presented at the conference.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Digital encoding algorithm for pixelated detectors

A detector for imaging and efficiently digitizing a spatial distribution of photon flux includes pixel circuits that compressively encode pixel values generated by integrated analog to digital converters (ADCs). On-pixel digital compression circuits (DCCs) implement compression to increase continuous frame rate by reducing the number of bits per pixel while keeping quantization error below Poisson noise. Several mapping algorithms for photon-counting and charge-integrating detectors and compact digital logic implementations are presented.

Hammer, Michael P.↗

Solar Neutrino Detection with a Pixelated Liquid-Argon Time Projection Chamber

This thesis presents a study of low-energy solar neutrino detection using large-scale LArTPCs, focussing on novel pixelated readout technologies. Solar neutrinos offer a unique probe of fundamental neutrino properties and solar physics, but their detection in the MeV range is challenged by backgrounds. We investigate two complementary technologies: SoLAr, which integrates LArPix-based pixelated charge collection with Silicon Photomultipliers (SiPMs) in a hybrid anode design for simultaneous charge and light detection; and Q-Pix, a triggerless pixelated readout architecture based on charge integrate-reset circuits with local clocks, where Reset Time Differences encode ionisation waveforms via time-to-charge conversion. Two SoLAr prototypes were developed and operated, demonstrating VUV-sensitive SiPM performance in liquid argon and accurate charge-light signal matching with a charge detection threshold of $\sim 100 \mathrm{keV}$. We also implement a complete simulation and reconstruction framework, incorporating realistic detector geometry, electron transport, readout response, and detailed signal and background models, including intrinsic argon and radon progeny, as well as site-specific $\gamma$-ray and neutron fluxes. For Q-Pix, we demonstrate that with a pixel size of $4\times 4$ mm$^2$ and a reset threshold of 1 fC ($\sim 0.1475$ MeV), full-scale operation produces data volumes below 1 PB per 10 ktonne-year. For SoLAr, assuming a shielded DUNE-like detector and 100 ktonne-year exposure, we project uncertainties of $0.90\times 10^{-5}$ eV$^2$ on $\Delta m^2_{21}$ and 0.033 on $\sin^2\theta_{12}$, improving to $0.46\times 10^{-5}$ eV$^2$ and 0.025 with 400 kilotonne-year. At this higher exposure, we also obtain a day–night flux asymmetry at the level of $( -5.6 \pm 3.6 ) \%$. Combining Monte Carlo modelling, hardware validation, and advanced reconstruction techniques, this work establishes a path toward next-generation ktonne-scale LArTPCs as observatories for precision solar neutrino physics.

Ruiz Ferreira, Guilherme [Manchester U.] (ORCID:00↗

A review of advances in pixel detectors for experiments with high rate and radiation

The large Hadron collider (LHC) experiments ATLAS and CMS have established hybrid pixel detectors as the instrument of choice for particle tracking and vertexing in high rate and radiation environments, as they operate close to the LHC interaction points. With the high luminosity-LHC upgrade now in sight, for which the tracking detectors will be completely replaced, new generations of pixel detectors are being devised. They have to address enormous challenges in terms of data throughput and radiation levels, ionizing and non-ionizing, that harm the sensing and readout parts of pixel detectors alike. Advances in microelectronics and microprocessing technologies now enable large scale detector designs with unprecedented performance in measurement precision (space and time), radiation hard sensors and readout chips, hybridization techniques, lightweight supports, and fully monolithic approaches to meet these challenges. In conclusion, this paper reviews the world-wide effort on these developments.

47 OTHER INSTRUMENTATION↗

Strategies for on-chip digital data compression for X-ray pixel detectors

Here, the continued desire for X-ray pixel detectors with higher frame rates will stress the ability of application-specific integrated circuit (ASIC) designers to provide sufficient off-chip bandwidth to reach continuous frame rates in the 1 MHz regime. To move from the current 10 kHz to the 1 MHz frame rate regime, ASIC designers will continue to pack as many power-hungry high-speed transceivers at the periphery of the ASIC as possible. In this paper, however, we present new strategies to make the most efficient use of the off-chip bandwidth by utilizing data compression schemes for X-ray photon-counting and charge-integrating pixel detectors. In particular, we describe a novel in-pixel compression scheme that converts from analog to digital converter units to encoded photon counts near the photon Poisson noise level and achieves a compression ratio of >1.5x independent of the dataset. In addition, we describe a simple yet efficient zero-suppression compression scheme called "zeromask" (ZM) located at the ASIC's edge before streaming data off the ASIC chip. ZM achieves average compression ratios of >4x, >7x, and >8x for high-energy X-ray diffraction, ptychography, and X-ray photon correlation spectroscopy datasets, respectively. We present the conceptual designs, register-transfer level block diagrams, and the physical ASIC implementation of these compression schemes in 65 nm CMOS. When combined, these two digital compression schemes could increase the effective off-chip bandwidth by a factor of 6-12x.

47 OTHER INSTRUMENTATION↗

A 65 nm CMOS analog processor with zero dead time for future pixel detectors

Next generation pixel chips at the High-Luminosity (HL) LHC will be exposed to extremely high levels of radiation and particle rates. In the so-called Phase II upgrade, ATLAS and CMS will need a completely new tracker detector, complying with the very demanding operating conditions and the delivered luminosity (up to 5×10 34 cm –2 s –1 in the next decade). This work is concerned with the design of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier featuring a detector leakage compensation circuit, and a compact, single ended comparator that guarantees very good performance in terms of channel-to-channel dispersion of threshold without needing any pixel-level trimming. A flash ADC is exploited for digital conversion immediately after the charge amplifier. In conclusion, a thorough discussion on the design of the charge amplifier and the comparator is provided along with an exhaustive set of simulation results.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Prototypes and system test stands for the Phase 1 upgrade of the CMS pixel detector

The CMS pixel phase-1 upgrade project replaces the current pixel detector with an upgraded system with faster readout electronics during the extended year-end technical stop of 2016/2017. New electronics prototypes for the system have been developed, and tests in a realistic environment for a comprehensive evaluation are needed. A full readout test stand with either the same hardware as used in the current CMS pixel detector or the latest prototypes of upgrade electronics has been built. The setup enables the observation and investigation of a jitter increase in the data line associated with trigger rate increases. This effect is due to the way in which the clock and trigger distribution is implemented in CMS. A new prototype of the electronics with a PLL based on a voltage controlled quartz crystal oscillator (QPLL), which works as jitter filter, in the clock distribution path was produced. With the test stand, it was confirmed that the jitter increase is not seen with the prototype, and also good performance was confirmed at the expected detector operation temperature ($-$20 °C).

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

The STAR MAPS-based PiXeL detector

The PiXeL detector (PXL) for the Heavy Flavor Tracker (HFT) of the STAR experiment at RHIC is the first application of the state-of-the-art thin Monolithic Active Pixel Sensors (MAPS) technology in a collider environment. Here, custom built pixel sensors, their readout electronics and the detector mechanical structure are described in detail. Selected detector design aspects and production steps are presented. The detector operations during the three years of data taking (2014–2016) and the overall performance exceeding the design specifications are discussed in the conclusive sections of this work.

73 NUCLEAR PHYSICS AND RADIATION PHYSICS↗

The Timepix4 analog front-end design: Lessons learnt on fundamental limits to noise and time resolution in highly segmented hybrid pixel detectors

This manuscript describes the optimization of the front-end readout electronics for high granularity hybrid pixel detectors. The theoretical study aims at minimizing the noise and jitter. The model presented here is validated with both circuit post layout simulations and measurements on the Timepix4 Application Specific Integrated Circuit (ASIC). The analog front-end circuit and the procedure to optimize the dimensions of the main transistors are described with detail. The Timepix4 is the most recent ASIC designed in the framework of the Medipix4 Collaboration. It was manufactured in 65nm CMOS process, and consists of a four side buttable matrix of 448 × 512 pixels with 55µm pitch. The analog front-end has a gain of ~36mV/ke - when configured in High Gain Mode, and ~20mV/ke - when configured in Low Gain Mode. The Equivalent Noise Charge (ENC) is ~68e - rms and ~80e - rms in High Gain Mode and in Low Gain Mode respectively. In event driven mode the incoming hits can be time stamped within a ~ 200ps time bin and the chip can deal with a maximum flux of ~ 3.6MHzmm –2 s –1 . In photon counting mode, the chip can deal with up to ~ 5GHzmm –2 s –1 . The routine designed to optimize the Timepix4 front-end is then used to analyze the performance limits in terms of jitter and noise for Charge Sensitive Amplifiers in pixel detectors.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

Digital pixel test structures implemented in a 65 nm CMOS process

The ALICE ITS3 (Inner Tracking System 3) upgrade project and the CERN EP R&D on monolithic pixel sensors are investigating the feasibility of the Tower Partners Semiconductor Co. 65 nm process for use in the next generation of vertex detectors. The ITS3 aims to employ wafer-scale Monolithic Active Pixel Sensors thinned down to 20–40 µm and bent to form truly cylindrical half barrels. Among the first critical steps towards the realisation of this detector is to validate the sensor technology through extensive characterisation both in the laboratory and with in-beam measurements. The Digital Pixel Test Structure (DPTS) is one of the prototypes produced in the first sensor submission in this technology and has undergone a systematic measurement campaign whose details are presented in this article. The results confirm the goals of detection efficiency and non-ionising and ionising radiation hardness up to the expected levels for ALICE ITS3 and also demonstrate operation at + 20 °C and a detection efficiency of 99% for a DPTS irradiated with a dose of 10 15 1 MeV n eq cm -2 . Furthermore, spatial, timing and energy resolutions were measured at various settings and irradiation levels.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

The SparkPix-S ASIC for the sparsified readout of 1 MHz frame-rate X-ray cameras at LCLS-II: pixel design and simulation results

Exploiting the “sparse” nature of the information in XPCS (X-ray Photon Correlation Spectroscopy) and XSVS (Speckle Visibility Spectroscopy) experiments, we present the SparkPix-S, a 3-sides buttable Application Specific Integrated Circuit (ASIC) based on a sparsified readout strategy for large-format hybrid detectors. The SparkPix-S architecture, based on the successful ePix family, will be composed as follows: a front-end 2-D matrix of 384×352 square pixels with 50 µm pitch is arranged to match the dimensions of a PIN Si-sensor matrix; charge readout, signal shaping and amplitude discrimination is performed at pixel-level, by means of a low-power (<18 µW) analog processor, which, in case of an event, negotiates access to an analog bus placed every other column; on the chip periphery (balcony), the information on each bus is digitized by an array of successive approximation analog-to-digital converters (SAR-ADCs) running at 10 Msps; on the digital back-end the global logic will generate the output data stream using low-voltage differential signalling (LVDS). A first prototype of the SparkPix-S, with a reduced matrix size of 96×96 pixels, is currently under production on a 130 nm CMOS technology. Simulated performance results show an equivalent noise charge <60 el. r.m.s. at 1 MHz repetition rate, with a maximum input energy of 60 keV and capability to discriminate charge signals with equivalent energy as low as 900 eV.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗