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At least 199 records · Page 11

Bandwidth Efficient Wireless Digital Modem Developed

NASA Lewis Research Center has developed a digital approach for broadcasting highfidelity audio (nearly compact disk (CD) quality sound) in the commercial frequencymodulated (FM) broadcast band. This digital approach provides a means of achieving high data transmission rates with low hardware complexity--including low mass, size, and power consumption. Lewis has completed the design and prototype development of a bandwidth-efficient digital modem (modulator and demodulator) that uses a spectrally efficient modulation scheme: 16-ary rectangular quadrature amplitude modulation, or 16- ary QAM. The digital implementation is based strictly on inexpensive, commercial off-theshelf digital signal processing (DSP) hardware to perform up and down conversions and pulse shaping. The digital modem transmits data at rates up to 76 kilobits per second (kbps), which is almost 3 times faster than standard 28.8-kbps telephone modems. In addition, the modem offers improved power and spectral performance, flexible operation, and low-cost implementation.

Kifle, Muli↗

Limits on Achievable Dimensional and Photon Efficiencies with Intensity-Modulation and Photon-Counting Due to Non-Ideal Photon-Counter Behavior

An ideal intensity-modulated photon-counting channel can achieve unbounded photon information efficiencies (PIEs). However, a number of limitations of a physical system limit the practically achievable PIE. In this paper, we discuss several of these limitations and illustrate their impact on the channel. We show that, for the Poisson channel, noise does not strictly bound PIE, although there is an effective limit, as the dimensional information efficiency goes as e[overline] e PIE beyond a threshold PIE. Since the Holevo limit is bounded in the presence of noise, this illustrates that the Poisson approximation is invalid at large PIE for any number of noise modes. We show that a finite transmitter extinction ratio bounds the achievable PIE to a maximum that is logarithmic in the extinction ratio. We show how detector jitter limits the ability to mitigate noise in the PPM signaling framework. We illustrate a method to model detector blocking when the number of detectors is large, and illustrate mitigation of blocking with spatial spreading and altering. Finally, we illustrate the design of a high photon efficiency system using state-of-the-art photo-detectors and taking all these effects into account.

quantum limited communications↗

Diagnosing and overcoming recombination and resistive losses in non-silicon solar cells using a silicon-inspired characterization platform

This project aimed to generate the characterization tools needed for accurate and systematic loss analysis in non-silicon photovoltaic solar cell technologies and, through the use of these tools and analysis techniques, contribute to the development of a novel class of hetero-contacts to II-VI absorbers, with the final goal of demonstrating record-breaking CdSeTe devices. CdSeTe solar cells provide a prime example of the potential impact of the techniques we proposed to develop and implement: record poly-CdSeTe cells have bandgap-voltage deficits (W oc ) of approximately 550 mV, as compared with below 400 mV for all other mature PV technologies. Similarly, these record CdSeTe devices have FFs below 80%, when other mature cells are near or above 85%. Frustratingly, a systematic identification of the origin of these sub-par performances—for example recombination or resistive losses—has been lacking, thus slowing down the development of these technologies. Similarly, it is often asserted that CdSeTe cells need a better back (hole) contact. Although most believe this is true, no one knew—at the start of this project—how high the V oc and FF could be for a given cell if it had a perfect back contact. Such characterization techniques and loss analysis methods exist and are routinely performed on c-Si solar cells (e.g. injection-dependent lifetime, Suns-V oc , transfer length method, etc). Over the years, they have been instrumental in the development of silicon devices that operate at 91% of their theoretical (Auger) limit. Lifetime testing, and the associated reconstruction of the implied-J-V curve, can moreover be performed at every cell-processing step, thus allowing a direct peek into the impact of that step on cell performance. Therefore, adapting these techniques and tools to non-Si devices would greatly improve their learning rate. In this project, we developed a Suns-ERE technique—the equipment, methodology, and know-how—to measure the implied-J-V curve, the pseudo-J-V curve, and the actual J-V curve of a thin-film solar cell, allowing an accurate assessment of the quality of the bulk material and its surface passivation, the selectivity of the contact, and its resistivity. We used this technique to show that the absorber of present CdSeTe solar cells is capable of achieving 1 V Voc,, that passivation layers exist (e.g., Al2O3) that can support such high voltages, and that the barrier is identifying contact layers that are both passivating and carrier-selective. The characterization platform created in this project and the understanding generated using it will accelerate the progress of non-silicon PV technologies. In particular, the project will contribute to CdSeTe solar cells with Voc > 1 V and cell efficiency > 24%. Such cells provide a pathway to module-level efficiencies >23%. As CdSeTe presently competes with silicon on module cost (in $\$ $/W) and yet has significantly more room for efficiency gains, the potential for LCOE reduction is particularly large. For example, CdTe modules with an efficiency of 21% would allow an LCOE below $\$ $0.04kWh -1 in average US climates.

14 SOLAR ENERGY↗

Low cost high efficiency GaAs monolithic RF module for SARSAT distress beacons

Low cost high performance (5 Watts output) 406 MHz beacons are urgently needed to realize the maximum utilization of the Search and Rescue Satellite-Aided Tracking (SARSAT) system spearheaded in the U.S. by NASA. Although current technology can produce beacons meeting the output power requirement, power consumption is high due to the low efficiency of available transmitters. Field performance is currently unsatisfactory due to the lack of safe and reliable high density batteries capable of operation at -40 C. Low cost production is also a crucial but elusive requirement for the ultimate wide scale utilization of this system. Microwave Monolithics Incorporated (MMInc.) has proposed to make both the technical and cost goals for the SARSAT beacon attainable by developing a monolithic GaAs chip set for the RF module. This chip set consists of a high efficiency power amplifier and a bi-phase modulator. In addition to implementing the RF module in Monolithic Microwave Integrated Circuit (MMIC) form to minimize ultimate production costs, the power amplifier has a power-added efficiency nearly twice that attained with current commercial technology. A distress beacon built using this RF module chip set will be significantly smaller in size and lighter in weight due to a smaller battery requirement, since the 406 MHz signal source and the digital controller have far lower power consumption compared to the 5 watt power amplifier. All the program tasks have been successfully completed. The GaAs MMIC RF module chip set has been designed to be compatible with the present 406 MHz signal source and digital controller. A complete high performance low cost SARSAT beacon can be realized with only additional minor iteration and systems integration.

Petersen, W. C.↗

The Description and Validation of a Computationally-Efficient CH4-CO-OH (ECCOH) Module for 3D Model Applications

We present the Efficient CH4-CO-OH Module (ECCOH) that allows for the simulation of the methane, carbon monoxide and hydroxyl radical (CH4-CO-OH cycle, within a chemistry climate model, carbon cycle model, or earth system model. The computational efficiency of the module allows many multi-decadal, sensitivity simulations of the CH4-CO-OH cycle, which primarily determines the global tropospheric oxidizing capacity. This capability is important for capturing the nonlinear feedbacks of the CH4-CO-OH system and understanding the perturbations to relatively long-lived methane and the concomitant impacts on climate. We implemented the ECCOH module into the NASA GEOS-5 Atmospheric Global Circulation Model (AGCM), performed multiple sensitivity simulations of the CH4-CO-OH system over two decades, and evaluated the model output with surface and satellite datasets of methane and CO. The favorable comparison of output from the ECCOH module (as configured in the GEOS-5 AGCM) with observations demonstrates the fidelity of the module for use in scientific research.

Remote Sensing↗

Scalable Two–Step Production of High–Efficiency Perovskite Solar Cells and Modules

Perovskite solar cells (PSCs) fabricated in laboratories have already achieved power conversion efficiency (PCE) comparable to market-dominant crystalline silicon solar cells. However, this promising photovoltaic technology suffers from severe loss of PCE during scaling up, limiting its progress toward commercialization. One critical question is to develop scalable, low-cost, high throughput, and well-controlled production methods to deposit high-quality perovskite films. Among various approaches, two-step sequential deposition methods have their unique advantages but have been long overlooked. This review provides an overview of two-step methods for fabricating efficient and stable perovskite solar modules (PSMs). We first discuss the mechanisms of two-step perovskite conversion and advanced engineering approaches to modulate the perovskite formation process. We survey the progress of efficient PSCs prepared by different two-step methods and compare the advantages and disadvantages of each method for scalable production of PSMs. Particularly, we highlight that the vapor-based two-step methods are promising for high-throughput in-line production of PSMs. Finally, we provide insights into the challenges and outlook of the industrialization of two-step processes for producing PSMs.

14 SOLAR ENERGY↗

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing, a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study, which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating, and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RNI subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a hi ch data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second(Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high- speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗

Architecture and implementation considerations of a high-speed Viterbi decoder for a Reed-Muller subcode

The (64, 40, 8) subcode of the third-order Reed-Muller (RM) code for high-speed satellite communications is proposed. The RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. The progress made toward achieving the goal of implementing a decoder system based upon this code is summarized. The development of the integrated circuit prototype sub-trellis IC, particularly focusing on the design methodology, is addressed.

Lin, Shu↗

Combinatorial FSK modulation for power-efficient high-rate communications

Deep-space and satellite communications systems must be capable of conveying high-rate data accurately with low transmitter power, often through dispersive channels. A class of noncoherent Combinatorial Frequency Shift Keying (CFSK) modulation schemes is investigated which address these needs. The bit error rate performance of this class of modulation formats is analyzed and compared to the more traditional modulation types. Candidate modulator, demodulator, and digital signal processing (DSP) hardware structures are examined in detail. System-level issues are also discussed.

Wagner, Paul K.↗

Combinatorial FSK modulation for power-efficient high-rate communications

Deep-space and satellite communications systems must be capable of conveying high-rate data accurately with low transmitter power, often through dispersive channels. A class of noncoherent Combinatorial Frequency Shift Keying (CFSK) modulation schemes is investigated which address these needs. The bit error rate performance of this class of modulation formats is analyzed and compared to the more traditional modulation types. Candidate modulator, demodulator, and digital signal processing (DSP) hardware structures are examined in detail. System-level issues are also discussed.

Wagner, Paul K.↗

Dual-module humidity pump for efficient air dehumidification: Demonstration and performance limitations

Condensation dehumidification in conventional air conditioning technologies is energy-intensive, accounting for up to 50% of building cooling energy used in some climates. Selective vacuum membrane dehumidification (VMD) is one of the leading alternative dehumidification technologies due to its potential for significant energy savings, and the “dual-module humidity pump” is one of the most promising VMD concepts. Here, this work is the first to provide experimental proof-of-concept for the dual-module humidity pump system and provides the first thermodynamic modeling framework that accounts for realistic steady-state operating limitations, both of which are lacking in the current literature. Additionally, this work is the first to provide a system design solution that overcomes practical challenges associated with air accumulation in the vacuum channels. The experimental results in this work show that the current prototype can remove up to 45% of the water vapor in the air stream, and the vapor pressure difference in the vapor rejection module needs to be approximately 2–4 times greater than that of the dehumidification module in order to maintain balanced mass transfer. The thermodynamic model applied to typical air conditioning conditions shows that the ideal dehumidification (latent) COPs can reach up to 40, but practical COPs are limited to approximately 10. Furthermore, the model shows that the overall energy efficiency increases as the membrane air selectivity increases, though this improvement gradually starts to diminish when the membrane selectivity is increased above 10,000.

32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗

A thermotropic liquid crystal enables efficient and stable perovskite solar modules

Perovskite solar cells have seen impressive progress in performance and stability, yet maintaining efficiency while scaling area remains a challenge. Here we find that additives commonly used to passivate large-area perovskite films often co-precipitate during perovskite crystallization and aggregate at interfaces, contributing to defects and to spatial inhomogeneity. Here we develop design criteria for additives to prevent their evaporative precipitation and enable uniform passivation of defects. We explored liquid crystals with melting point below the perovskite processing temperature, functionalization for defect passivation and hydrophobicity to improve device stability. We find that thermotropic liquid crystals such as 3,4,5-trifluoro-4'-(trans-4-propylcyclohexyl)biphenyl enable large-area perovskite films that are uniform, low in defects and stable against environmental stress factors. We demonstrate modules with a certified stabilized efficiency of 21.1% at an aperture area of 31 cm 2 and enhanced stability under damp-heat conditions (ISOS-D-3, 85% relative humidity, 85 °C) with T 86 (the duration for the efficiency to decay to 86% of the initial value) of 1,200 h, and reverse bias with (ISOS-V-1, negative maximum-power-point voltage) and without bypass diodes.

14 SOLAR ENERGY↗

Lightweight concentrator module with 30 percent AM0 efficient GaAs/GaSb tandem cells

A concept is presented for an aerospace concentrator module with lightweight domed lenses and 30 percent AM0 efficient GaAs/GaSb tandem solar cell circuits. The performance of transparent GaAs cells is reviewed. NASA's high-altitude jet flight calibration data for recent GaSb cells assembled with bulk GaAs filters are reported, along with subsequent Boeing and NASA measurements of GaSb I-V performance at various light levels and temperatures. The expected performance of a basic two-terminal tandem concentrator circuit with three-to-one voltage matching is discussed. All of the necessary components being developed to assemble complete flight test coupons are shown. Straightforward interconnect and assembly techniques yield voltage matched circuits with near-optimum performance over a wide temperature range.

Avery, J. E.↗