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At least 199 records · Page 11

Radiation Failures in Intel 14nm Microprocessors

In this study the 14 nm Intel Broadwell 5th generation core series 5005U-i3 and 5200U-i5 was mounted on Dell Inspiron laptops, MSI Cubi and Gigabyte Brix barebones and tested with Windows 8 and CentOS7 at idle. Heavy-ion-induced hard- and catastrophic failures do not appear to be related to the Intel 14nm Tri-Gate FinFET process. They originate from a small (9 m 140 m) area on the 32nm planar PCH die (not the CPU) as initially speculated. The hard failures seem to be due to a SEE but the exact physical mechanism has yet to be identified. Some possibilities include latch-ups, charge ion trapping or implantation, ion channels, or a combination of those (in biased conditions). The mechanism of the catastrophic failures seems related to the presence of electric power (1.05V core voltage). The 1064 nm laser mimics ionization radiation and induces soft- and hard failures as a direct result of electron-hole pair production, not heat. The 14nm FinFET processes continue to look promising for space radiation environments.

Microprocessors↗

Single-event upset in the PowerPC750 microprocessor

In this paper we report results of single-event tests of the PowerPC750 from Motorola and IBM, which are identical designs which are manufactured with advanced processes that uses a minimum feature size of 0.29 and 0.28 mu m, respectively.

single↗

The application of microprocessors to strapdown inertial navigation

The fundamental concepts of inertial navigation are briefly examined. In a strapdown inertial navigator the accelerometers and gyros are mounted directly on the vehicle frame. The development of strapdown systems, which have important advantages over gimbal systems, has been mainly retarded by the computational requirements involved. However, the current availability of suitable minicomputers combined with other technological advances has now opened the way for a more widespread use of strapdown inertial navigators.

Napjus, G. A.↗

Test program for 4-K memory card, JOLT microprocessor

A memory test program is described for use with the JOLT microcomputer 4,096-word memory board used in development of an Omega navigation receiver. The program allows a quick test of the memory board by cycling the memory through all possible bit combinations in all words.

Lilley, R. W.↗

A keyboard interface for the JOLT microprocessor

A keyboard interface designed to allow data input without use of a teleprinter is described. In operation, the keyboard allows JOLT start-up and entry of data for LORAN or OMEGA navigation.

Wright, L.↗

A distributed microprocessor system for spacecraft control and data handling

The specific requirements for spacecraft computing systems are considered. These requirements are partly related to the constraints of limited resources of power, weight, and volume. Another important factor is the requirement of extremely high reliability. These reliability requirements have led to introduction of automated redundancy techniques on board the spacecraft. The various redundant computers check each other and provide recovery procedures when a computer is found to have failed. Past and future capabilities are considered along with distributed processing requirements. System considerations are discussed, taking into account suboptimum computer throughput, sensitivity to software modifications, hierarchic timing, I/O granularity, restricted communications, synchronous functions, hierarchic control, and concurrent error detection. A description is presented of the Unified Data System (UDS), which consists of a set of standard microcomputers connected by several buses. Attention is also given to synchronization and timing, the executive control structure, the programming language, and the executive program.

Rennels, D. A.↗

Microprocessor control for standardized power control systems

The use of microcomputers in space-oriented power systems as a replacement for existing inflexible analog type controllers has been proposed. This study examines multiprocessor systems, various modularity concepts and presents a conceptualized power system incorporating a multiprocessor controller as well as preliminary results from a breadboard model of the proposed system.

Green, D. G.↗

A versatile microprocessor-controlled hybrid receiver

A hybrid receiver has been designed for the Galileo Project. The receiver, located on the Galileo Orbiter, will autonomously acquire and track signals from the first atmospheric probe of Jupiter as well as demodulate, bit-synchronize, and buffer the telemetry data. The receiver has a conventional RF and LF front end but performs multiple functions digitally under firmware control. It will be a self-acquiring receiver that operates under a large frequency uncertainty; it can accommodate different modulation types, bit rates, and other parameter changes via reprogramming. A breadboard receiver and test set demonstrate a preliminary version of the sequential detection process and verify the hypothesis that a fading channel does not reduce the probability of detection.

Grant, T. L.↗

Simulation of distributed microprocessor-based flight control systems

The aim of the present paper is to demonstrate, within the framework of a digital flight control system, the method of simulating the information exchange between a microcomputer and a supervisory computer, and between microcomputers working on separate control tasks. A gradient technique is described that considers the trade-off between the objectives of the control system and the information exchange requirements.

Lee, P. S.↗

Microprocessor-controlled data synchronizer

Versatile receiver processes data at variety of rates and code formats. Functions performed are: bit detection, NRZ-L conversion, frame synchronization (with programmable word length), bit-sync acquisition and tracking, error-curve normalization, lock detection, half-bit-ambiguity resolution, and data-rate tracking.

Houston, S. W.↗

Microprocessor control for phase-lock receiver

Subsystem facilities flexible data acquisition by combining hardware and software processing. Device controls complex signal acquisition sequence and assists in precise phase locking to received signal. Key features include software system and code-generator initialization routines, executive routine, utility subroutines, control sequence routines for each receiver acquisition state, control-command decoding routine, and look-up tables for code-generator configuration versus code-set number. Steps can be added to extend input signal dynamic range.

Carson, L. M.↗

Microprocessor-based detector for PSK commands

Command detector unit operates over wide range of data rates and signal levels in space environment. It consists of signal conditioning, read-only memory, random-access memory, and digital processor. Entire unit fits on single multilayer printed-wiring board.

Durden, J.↗

Microprocessor systems for industrial process control

Six computers operate synchronously and are interconnected by three independent data buses. Processors control one subsystem. Some can control buses to transfer data at 1 megabit per second. Every 2.5 msec each processor examines list of things to do during next interval. This spacecraft control system could be adapted for controlling complex industrial processes.

Lesh, F. H.↗

An experimental distributed microprocessor implementation with a shared memory communications and control medium

The distributed processing concept is defined in terms of control primitives, variables, and structures and their use in performing a decomposed discrete Fourier transform (DET) application function. The design assumes interprocessor communications to be anonymous. In this scheme, all processors can access an entire common database by employing control primitives. Access to selected areas within the common database is random, enforced by a hardware lock, and determined by task and subtask pointers. This enables the number of processors to be varied in the configuration without any modifications to the control structure. Decompositional elements of the DFT application function in terms of tasks and subtasks are also described. The experimental hardware configuration consists of IMSAI 8080 chassis which are independent, 8 bit microcomputer units. These chassis are linked together to form a multiple processing system by means of a shared memory facility. This facility consists of hardware which provides a bus structure to enable up to six microcomputers to be interconnected. It provides polling and arbitration logic so that only one processor has access to shared memory at any one time.

Mejzak, R. S.↗