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At least 199 records · Page 11

All sources NASA NTRS DOE OSTI

NASA NTRS1986

The effects of voice and manual control mode on dual task performance

Two fundamental principles of human performance, compatibility and resource competition, are combined with two structural dichotomies in the human information processing system, manual versus voice output, and left versus right cerebral hemisphere, in order to predict the optimum combination of voice and manual control with either hand, for time-sharing performance of a dicrete and continuous task. Eight right handed male subjected performed a discrete first-order tracking task, time-shared with an auditorily presented Sternberg Memory Search Task. Each task could be controlled by voice, or by the left or right hand, in all possible combinations except for a dual voice mode. When performance was analyzed in terms of a dual-task decrement from single task control conditions, the following variables influenced time-sharing efficiency in diminishing order of magnitude, (1) the modality of control, (discrete manual control of tracking was superior to discrete voice control of tracking and the converse was true with the memory search task), (2) response competition, (performance was degraded when both tasks were responded manually), (3) hemispheric competition, (performance degraded whenever two tasks were controlled by the left hemisphere) (i.e., voice or right handed control). The results confirm the value of predictive models invoice control implementation.

Wickens, C. D.↗

NASA NTRS1990

Rule-based mechanisms of learning for intelligent adaptive flight control

How certain aspects of human learning can be used to characterize learning in intelligent adaptive control systems is investigated. Reflexive and declarative memory and learning are described. It is shown that model-based systems-theoretic adaptive control methods exhibit attributes of reflexive learning, whereas the problem-solving capabilities of knowledge-based systems of artificial intelligence are naturally suited for implementing declarative learning. Issues related to learning in knowledge-based control systems are addressed, with particular attention given to rule-based systems. A mechanism for real-time rule-based knowledge acquisition is suggested, and utilization of this mechanism within the context of failure diagnosis for fault-tolerant flight control is demonstrated.

Handelman, David A.↗

NASA NTRS1976

In-flight utilization of the Mariner 10 spacecraft computer

Mariner 10 in its mission to Venus and Mercury used an onboard control computer with a 512-word memory. An outline is presented of the general philosophy adopted with respect to the utilization of the available memory and a description is given of the actual in-flight operation of the machine. The onboard computer system provided automatic stored-program sequence control of all spacecraft scientific, engineering, and propulsive maneuver operations. The system consisted of the special purpose digital computer and a fixed hard-wired sequencer. Attention is given to the programming architecture, aspects of mission design, and computer performance.

Hooke, A. J.↗

NASA NTRS1985

Programable Driver for Voltage-Controlled Oscillators

Electronically programable read-only memory (EPROM) and digital-to-analog converter provide customized time-varying voltage for frequency modulation. Voltage used to modulate IMPATT oscillator that serves as microwave pump for solid-state maser in low-noise amplifier. EPROM simple to tailor voltage waveform to suit characteristics of given maser. Digital information for waveform programed into EPROM chip; digital-to-analog converter reads information and produces corresponding analog wave. Principle readily adapted to other applications.

Fowler, L. E.↗

NASA NTRS1972

Design, processing, and testing of lsi arrays for space station

The design of a MOS 256-bit Random Access Memory (RAM) is discussed. Technological achievements comprise computer simulations that accurately predict performance; aluminum-gate COS/MOS devices including a 256-bit RAM with current sensing; and a silicon-gate process that is being used in the construction of a 256-bit RAM with voltage sensing. The Si-gate process increases speed by reducing the overlap capacitance between gate and source-drain, thus reducing the crossover capacitance and allowing shorter interconnections. The design of a Si-gate RAM, which is pin-for-pin compatible with an RCA bulk silicon COS/MOS memory (type TA 5974), is discussed in full. The Integrated Circuit Tester (ICT) is limited to dc evaluation, but the diagnostics and data collecting are under computer control. The Silicon-on-Sapphire Memory Evaluator (SOS-ME, previously called SOS Memory Exerciser) measures power supply drain and performs a minimum number of tests to establish operation of the memory devices. The Macrodata MD-100 is a microprogrammable tester which has capabilities of extensive testing at speeds up to 5 MHz. Beam-lead technology was successfully integrated with SOS technology to make a simple device with beam leads. This device and the scribing are discussed.

Lile, W. R.↗

NASA NTRS1981

The Lick Observatory charge-coupled device /CCD/ and controller

A description is given of a flexible microprocessor-based controller for charge-coupled device two-dimensional detectors. It is noted that the controller can operate under manual control or as a slave to a remote computer linked by coaxial cable. The system is discussed, together with data taken at the telescope and in the laboratory. The flexibility of the controller derives from its modular form and from the use of a programmable 8-bit microprocessor to control and sequence the electronic logic. The electronic circuits for such functions as signal processing, clock sequencing, voltage level adjustment, and temperature control are on small individual plug-in cards, making future improvements and changes simple. The software of the microprocessor is stored in erasable, programmable, read-only memory. Among the limitations of the controller is a scan speed of roughly 35 microsec per pixel.

Robinson, L. B.↗

NASA NTRS1978

A wide bandwidth CCD buffer memory system

A prototype system was implemented to demonstrate that CCD's can be applied advantageously to the problem of low power digital storage and particularly to the problem of interfacing widely varying data rates. CCD shift register memories (8K bit) were used to construct a feasibility model 128 K-bit buffer memory system. Serial data that can have rates between 150 kHz and 4.0 MHz can be stored in 4K-bit, randomly-accessible memory blocks. Peak power dissipation during a data transfer is less than 7 W, while idle power is approximately 5.4 W. The system features automatic data input synchronization with the recirculating CCD memory block start address. System expansion to accommodate parallel inputs or a greater number of memory blocks can be performed in a modular fashion. Since the control logic does not increase proportionally to increase in memory capacity, the power requirements per bit of storage can be reduced significantly in a larger system.

Siemens, K.↗

NASA NTRS1977

Packaging of a large capacity magnetic bubble domain spacecraft recorder

A Solid State Spacecraft Data Recorder (SSDR), based on bubble domain technology, having a storage capacity of 10 to the 8th power bits, was designed and is being tested. The recorder consists of two memory modules each having 32 cells, each cell containing sixteen 100 kilobit serial bubble memory chips. The memory modules are interconnected to a Drive and Control Unit (DCU) module containing four microprocessors, 500 integrated circuits, a RAM core memory and two PROM's. The two memory modules and DCU are housed in individual machined aluminum frames, are stacked in brick fashion and through bolted to a base plate assembly which also houses the power supply.

Becker, F. J.↗

NASA NTRS1974

Metallic oxide switches using thick film technology

Metallic oxide thick film switches were processed on alumina substrates using thick film technology. Vanadium pentoxide in powder form was mixed with other oxides e.g., barium, strontium copper and glass frit, ground to a fine powder. Pastes and screen printable inks were made using commercial conductive vehicles and appropriate thinners. Some switching devices were processed by conventional screen printing and firing of the inks and commercial cermet conductor terminals on 96% alumina substrates while others were made by applying small beads or dots of the pastes between platinum wires. Static, and dynamic volt-ampere, and pulse tests indicate that the switching and self-oscillatory characteristics of these devices could make them useful in memory element, oscillator, and automatic control applications.

Patel, D. N.↗

NASA NTRS1975

Preliminary data processing system for telemetry data from Interkosmos-8 type satellites

The preliminary data processing system (PDPS), a set of algorithms, programs, equipment, data storage and memory devices, and all devices controlling the processing, is described using the Intercosmos-8 satellite as an example. Each stage of the system is considered along with its content and sequence. The essential elements of the data processing structure are described and the concepts underlying the selection of these elements are discussed.

Vilchinskaya, A. S.↗

NASA NTRS1976

Digital video image system

Interactive recording and display device acts as very-high-speed data-input/output interface between analog (video) signals and standard digital-computer components. System can be used with various picture and memory sizes and can be controlled manually or by computer.

Neely, P. L.↗

NASA NTRS1975

Design of a modular digital computer system, CDRL no. D001, final design plan

The engineering breadboard implementation for the CDRL no. D001 modular digital computer system developed during design of the logic system was documented. This effort followed the architecture study completed and documented previously, and was intended to verify the concepts of a fault tolerant, automatically reconfigurable, modular version of the computer system conceived during the architecture study. The system has a microprogrammed 32 bit word length, general register architecture and an instruction set consisting of a subset of the IBM System 360 instruction set plus additional fault tolerance firmware. The following areas were covered: breadboard packaging, central control element, central processing element, memory, input/output processor, and maintenance/status panel and electronics.

Easton, R. A.↗

NASA NTRS1977

Efficient bit-error detecting code

Two highly reliable codes termed "Modified b-adjacent interleaving codes" provide fail-safe operation of launch processing and control system in which common memory is coordination point for interconnection of up to 64 minicomputers. Codes detect and correct bit errors in computer data transmission.

Hockenberger, R. W.↗

NASA NTRS1976

Intensified charge coupled devices for ultra low light level imaging

Development of a sensor incorporating a CCD and photocathode for operation in the electron bombarded mode in both a magnetic and an electrostatic focussed, gated configuration is described. Initial format size is 100 x 160 pixels with eventual growth to 400 x 400 pixels. The sensor is part of a digital camera system which includes the low level video conditioning electronics, a camera controller, a high speed buffer memory, and digital recording and display electronics. The memory uses CMOS/SOS and has a capacity of 1.6 Mbits with operating rates of 48 Mbits/sec. Individual frames are co-added to provide wide dynamic range and photometric precision better than 1%. A 4-bit video quantization is used to increase the photon counting detection rate before coincidence losses become serious.

Sobieski, S.↗

NASA NTRS1981

Development of a fault-tolerant microprocessor based computer system for space flight

A methodology for the design of a tightly coupled, highly reliable microprocessor based computer system is described. The concept of triple modular redundancy with sparing is used. The notion of synchronizing by using a single crystal oscillator is examined. The use of decoders to replace voters is also used. The decoders not only isolate the failed module but also allow error identification to be accomplished. Each module is to have its own RAM memory. The necessary circuitry to select a correct memory and the corresponding DMA controller was designed.

Montgomery, V. T.↗

NASA NTRS1990

A scheme for supporting distributed data structures on multicomputers

A data migration mechanism is proposed that allows an explicit and controlled mapping of data to memory. While read or write copies of each data element can be assigned to any processor's memory, longer term storage of each data element is assigned to a specific location in the memory of a particular processor. The proposed integration of a data migration scheme with a compiler is able to eliminate the migration of unneeded data that can occur in multiprocessor paging or caching. The overhead of adjudicating multiple concurrent writes to the same page or cache line is also eliminated. Data is presented that suggests that the scheme may be a pratical method for efficiently supporting data migration.

Hiranandani, Seema↗

NASA NTRS1990

A scheme for supporting automatic data migration on multicomputers

Mirchandaney, Seema↗

NASA NTRS1990

Free float acceleration measurements aboard NASA's KC-135 Microgravity Research Aircraft

A three-axis accelerometer subsystem, developed as part of a get-away-special Ga-As crystal growth system for the Space Shuttle, is described. Each axis of this subsystem contains a quartz flexure accelerometer capable of dc measurements, custom-designed measurement circuitry, a programmable microcomputer for measurement control and data reduction, and memory for recording data. The subsystem was flown as a free float experiment aboard the NASA KC-135 microgravity research aircraft, yielding measurements of accelerations during free float at a resolution of 10 micro-g.

Bellows, A. H.↗