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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 199 records · Page 11
All sourcesNASA NTRSDOE OSTI
NASA NTRS1990

Computation and parallel implementation for early vision

The problem of early vision is to transform one or more retinal illuminance images-pixel arrays-to image representations built out of such primitive visual features such as edges, regions, disparities, and clusters. These transformed representations form the input to later vision stages that perform higher level vision tasks including matching and recognition. Researchers developed algorithms for: (1) edge finding in the scale space formulation; (2) correlation methods for computing matches between pairs of images; and (3) clustering of data by neural networks. These algorithms are formulated for parallel implementation of SIMD machines, such as the Massively Parallel Processor, a 128 x 128 array processor with 1024 bits of local memory per processor. For some cases, researchers can show speedups of three orders of magnitude over serial implementations.

Gualtieri, J. Anthony↗
NASA NTRS2000

Quantitative Analysis of Charge Injection and Discharging of Si Nanocrystals and Arrays by Electrostatic Force Microscopy

NASA requirements for computing and memory for microspacecraft emphasize high density, low power, small size, and radiation hardness. The distributed nature of storage elements in nanocrystal floating-gate memories leads to intrinsic fault tolerance and radiation hardness. Conventional floating-gate non-volatile memories are more susceptible to radiation damage. Nanocrystal-based memories also offer the possibility of faster, lower power operation. In the pursuit of filling these requirements, the following tasks have been accomplished: (1) Si nanocrystal charging has been accomplished with conducting-tip AFM; (2) Both individual nanocrystals on an oxide surface and nanocrystals formed by implantation have been charged; (3) Discharging is consistent with tunneling through a field-lowered oxide barrier; (4) Modeling of the response of the AFM to trapped charge has allowed estimation of the quantity of trapped charge; and (5) Initial attempts to fabricate competitive nanocrystal non-volatile memories have been extremely successful.

Bell, L. D.↗
NASA NTRS2000

Quantitative analysis of charge injection and discharging of Si nanocrystals and arrays by electrostatic force microscopy

NASA requirements for computing and memory for microspacecraft emphasizes high density, low power, small size, and radiation hardness. The distributed nature of a storage elements in nanocrystal floating-gate memories leads to instrinsic fault tolerance and radiation-hardness. Nanocrystal-based memories also offer the possibility of a faster, lower power operation.

atomic↗
DOE OSTI2024

Sum Reduction with OpenMP Offload on NVIDIA Grace-Hopper System

We evaluate the performance of the baseline and optimized reductions in OpenMP on an NVIDIA Grace-Hopper system. We explore the impacts of the number of teams, the number of elements to sum per loop iteration, and simultaneous execution on the central-processing unit (CPU) and the GPU in the unified memory (UM) mode upon the reduction performance. The experimental results show that the optimized reductions are 6.120X to 20.906X faster than the baselines on the GPU, and their efficiency ranges from 89% to 95% of the theoretical GPU memory bandwidth. Depending on where an input array is allocated in the program when co-running the reduction on the CPU and GPU in the UM mode, the average speedup over the GPU-only execution is approximately 2.484 or 1.067, and the speedup of the optimized reductions over the baseline reductions ranges from 0.996 to 10.654 or from 0.998 to 6.729.

Jin, Zheming↗
NASA NTRS1974

A membrane page composer - Further developments

Membrane page composers were made and were evaluated in a simulated holographic optical memory system. Calculated and experimentally determined electromechanical and optical characteristics of the circular membrane light valves used on the arrays are shown to be in close agreement. Several operating prototypes of 8 x 8 and 16 x 16 elements were produced. Measurements were made of switching time, optical contrast, and dynamic storage time of many cells on the devices. Digital patterns were stored in the arrays. The performance required of the page composer as a component of an optical memory system is considered. The fabrication techniques used can be easily extended to larger arrays.

Cosentino, L. S.↗
NASA NTRS1983

Array processor architecture

A high speed parallel array data processing architecture fashioned under a computational envelope approach includes a data base memory for secondary storage of programs and data, and a plurality of memory modules interconnected to a plurality of processing modules by a connection network of the Omega gender. Programs and data are fed from the data base memory to the plurality of memory modules and from hence the programs are fed through the connection network to the array of processors (one copy of each program for each processor). Execution of the programs occur with the processors operating normally quite independently of each other in a multiprocessing fashion. For data dependent operations and other suitable operations, all processors are instructed to finish one given task or program branch before all are instructed to proceed in parallel processing fashion on the next instruction. Even when functioning in the parallel processing mode however, the processors are not locked-step but execute their own copy of the program individually unless or until another overall processor array synchronization instruction is issued.

Barnes, George H.↗
NASA NTRS1977

The robot's eyes - Stereo vision system for automated scene analysis

Attention is given to the robot stereo vision system which maintains the image produced by solid-state detector television cameras in a dynamic random access memory called RAPID. The imaging hardware consists of sensors (two solid-state image arrays using a charge injection technique), a video-rate analog-to-digital converter, the RAPID memory, and various types of computer-controlled displays, and preprocessing equipment (for reflexive actions, processing aids, and object detection). The software is aimed at locating objects and transversibility. An object-tracking algorithm is discussed and it is noted that tracking speed is in the 50-75 pixels/s range.

Williams, D. S.↗
NASA NTRS1987

Rectification of terrain induced distortions in radar imagery

This paper describes a technique to generate geocoded synthetic aperture radar (SAR) imagery corrected for terrain induced geometric distortions. This algorithm transforms the raw slant range image, generated by the signal processor, into a map registered product, resampled to either Universal Transverse Mercator (UTM) or Polar Stereographic projections, and corrected for foreshortening. The technique utilizes the space platform trajectory information in conjunction with a digital elevation map (DEM) of the target area to generate an ortho-radar map with near-autonomous operation. The current procedure requires only two to three tie-points to compensate for the platform position uncertainty that results in translational error between the image and the DEM. This approach is unique in that it does not require generation of a simulated radar image from the DEM or a grid of tie-points to characterize the image-to-map distortions. Rather, it models the inherent distortions based on knowledge of the radar data collection characteristics, the signal Doppler parameters, and the local terrain height to automatically predict the registration transformation. This algorithm has been implemented on a minicomputer system equipped with an array processor and a large random-access memory to optimize the throughput.

Kwok, Ronald↗
NASA NTRS2000

Free-Flying Magnetometer Data System

The Free-Flying Magnetometer (FFM) is an autonomous "sensorcraft" developed at the Jet Propulsion Laboratory (JPL) for the Enstrophy sounding rocket mission. This mission was a collaborative project between the University of New Hampshire, Cornell University and JPL. The science goal of the mission was the study of current filamentation phenomena in the northern auroral region through multipoint measurements of magnetic field. The technical objective of the mission was the proof of concept of the JPL FFM design and the demonstration of an in-situ multipoint measurement technique employing many free-flying spacecraft. Four FFMs were successfully deployed from a sounding rocket launched from Poker Flats, Alaska on February 11, 1999. These hockey-puck-sized (80 mm diameter, 38 mm. height, 250 gram mass) free flyers each carry a miniature 3-axis flux-gate magnetometer that output +/- 2 V signals corresponding to a +/- 60,000 nT measurement range for each axis. The FFM uses a synchronized four-channel Sigma(Delta) Analog-to-Digital Converter (ADC) having a dynamic range of +/- 2.5V and converting at a rate of 279 samples/second/channel. Three channels are used to digitize the magnetometer signals to 17-bit (1.144 nT/bit) resolution. The fourth ADC channel is multiplexed for system monitoring of four temperature sensors and two battery voltages. The FFM also contains two sun sensors, a laser diode which emits a fan-shaped beam, a miniature S-band transmitter for direct communication to the ground station antennas, an ultra-stable Temperature Compensated Crystal Oscillator (TCXO) clock, an integrated data subsystem implemented in a Field-Programmable Gate Array (FPGA), a 4 Mbit Static Random Access Memory (SRAM) for data storage and Lithium Thionyl Chloride batteries for power. Communicating commands to the FFM prior to deployment is achieved with an infrared (IR) link. The FFM IR receiver responds to 9-bit pulse coded signals that are generated by an IR Light Emitting Diode (LED) in the payload for turning FFM power on or off and placing the FFM in a test mode or flight mode. The IR links are also used to synchronize (zero) the clocks onboard all the FFMs through a reset pulse originating from the payload GPS receiver that is issued when the FFMs are in flight mode. The FPGA based data subsystem manages continuous data collection from the four ADC channels and sun sensors, formatting and storing the data to SRAM, and controlling downlink transmission. The transmitter is powered only after a 2547 frame SRAM buffer has been filled (approx. 5 minutes of data). The data is Viterbi encoded and sent to the S-band transmitter via a First-In-First-Out (FIFO) buffer who's output is clocked at 100 bits/second. After the 26-second transmission, the transmitter is turned off to reduce noise coupling to the sensitive magnetometer. The data subsystem control consists of a master state machine that performs data flow management and is interfaced through a prioritized interrupt scheme to state machines that service the ADC, sun sensors and transmitter FIFO. Continuous data collection prevents the missing of data during transmission and provides implicit time tagging of the data acquired by the ADC because of synchronization with the TCXO clock.

Blaes, B.↗
NASA NTRS2000

JavaGenes and Condor: Cycle-Scavenging Genetic Algorithms

A genetic algorithm code, JavaGenes, was written in Java and used to evolve pharmaceutical drug molecules and digital circuits. JavaGenes was run under the Condor cycle-scavenging batch system managing 100-170 desktop SGI workstations. Genetic algorithms mimic biological evolution by evolving solutions to problems using crossover and mutation. While most genetic algorithms evolve strings or trees, JavaGenes evolves graphs representing (currently) molecules and circuits. Java was chosen as the implementation language because the genetic algorithm requires random splitting and recombining of graphs, a complex data structure manipulation with ample opportunities for memory leaks, loose pointers, out-of-bound indices, and other hard to find bugs. Java garbage-collection memory management, lack of pointer arithmetic, and array-bounds index checking prevents these bugs from occurring, substantially reducing development time. While a run-time performance penalty must be paid, the only unacceptable performance we encountered was using standard Java serialization to checkpoint and restart the code. This was fixed by a two-day implementation of custom checkpointing. JavaGenes is minimally integrated with Condor; in other words, JavaGenes must do its own checkpointing and I/O redirection. A prototype Java-aware version of Condor was developed using standard Java serialization for checkpointing. For the prototype to be useful, standard Java serialization must be significantly optimized. JavaGenes is approximately 8700 lines of code and a few thousand JavaGenes jobs have been run. Most jobs ran for a few days. Results include proof that genetic algorithms can evolve directed and undirected graphs, development of a novel crossover operator for graphs, a paper in the journal Nanotechnology, and another paper in preparation.

Globus, Al↗
NASA NTRSDate not supplied

Advanced eLectrical Bus (ALBus) CubeSat: From Build to Flight

Advanced eLectrical Bus (ALBus) CubeSat is a technology demonstration mission of a 3-U CubeSat with an advanced digitally controlled electrical power system and novel use of Shape Memory Alloy (SMA) technology for reliable deployable solar array mechanisms. The primary objective was to advance the power management and distribution (PMAD) capabilities to enable future missions requiring more flexible and reliable power systems with higher output power capabilities. Goals included demonstration of 100W distribution to a target electrical load, response to continuous and fast transient power requirements, and exhibition of reliable deployment of solar arrays and antennas utilizing re-settable SMA mechanisms. The power distribution function of the ALBus PMAD system is unique in the total power to target load capability, as power is distributed from batteries to provide 100W of power directly to a resistive load. The deployable solar arrays utilize NASA’s Nickel-Titanium-Palladium-Platinum (NiTiPdPt) high-temperature SMAs for the retention and release mechanism, and a superelastic binary NiTi alloy for the hinge component. The project launched as part of the CubeSat Launch Initiative (CLI) Educational Launch of Nanosatellites (ELaNa) XIX mission on Rocket Lab’s Electron in December 2018. This paper summarizes the final launched design and the lessons learned from build to flight.

Deboshri Sadhukhan↗
NASA NTRSDate not supplied

Advanced eLectrical Bus (ALBus) CubeSat: From Build to Flight

The Advanced eLectrical Bus (ALBus) CubeSat project is a technology demonstration mission of a 3-U CubeSat with an advanced, digitally controlled electrical power system capability and novel use of Shape Memory Alloy (SMA) technology for reliable deployable solar array mechanisms. The objective of the project was to advance the state of power management and distribution (PMAD) capabilities to enable future missions requiring flexible and reliable power systems with higher output power capabilities. The goals of the mission were to demonstrate 100W distribution to a target electrical load, respond to continuous and fast transient power requirements, and show reliable deployment of solar arrays and antennas utilizing re-settable SMA mechanisms. The power distribution function of the ALBus PMAD system is unique in the total power to target load capability. Power is distributed from batteries to provide 100W of power directly to a resistive load. The deployable solar arrays utilize NASA Glenn Research Center’s Nickel-Titanium-Palladium-Platinum high-temperature SMAs for the retention and release mechanism, and a super-elastic binary NiTi alloy for the hinge component. The deployable solar array hinge design features the utilization of SMA material properties for a dual purpose. First, the hinge uses the super-elastic SMA properties to provide the spring force to deploy the arrays. Second, the electrical conductivity properties of the SMA enables the design to provide clean conduits for power transfer from the deployable arrays to the power management system. This eliminates the need for electrical harnesses between the arrays and the PMAD system in the ALBus system design. The uniqueness of the SMA retention and release mechanism design is the ability to reset the mechanism and reuse the same hardware. This allow functional tests of the mechanisms before flight with no degradation of performance and flying the hardware that is tested. The project launched as part of the CubeSat Launch Initiative Educational Launch of Nanosatellites (ELaNa) XIX mission on Rocket Lab’s Electron in December 2018. This paper summarizes the final launched design of ALBus and lessons learned from the technology and overall project from development through flight.

Deboshri Sadhukhan↗
NASA NTRS1988

Arranging computer architectures to create higher-performance controllers

Techniques for integrating microprocessors, array processors, and other intelligent devices in control systems are reviewed, with an emphasis on the (re)arrangement of components to form distributed or parallel processing systems. Consideration is given to the selection of the host microprocessor, increasing the power and/or memory capacity of the host, multitasking software for the host, array processors to reduce computation time, the allocation of real-time and non-real-time events to different computer subsystems, intelligent devices to share the computational burden for real-time events, and intelligent interfaces to increase communication speeds. The case of a helicopter vibration-suppression and stabilization controller is analyzed as an example, and significant improvements in computation and throughput rates are demonstrated.

Jacklin, Stephen A.↗
DOE OSTI2021

MATAR: A performance portability and productivity implementation of data-oriented design with Kokkos

There is a need for simple, fast, and memory-efficient multidimensional data structures for dense and sparse storage that arise with numerical methods and in software applications. The data structures must perform equally well across multiple computer architectures, including CPUs and GPUs. For this purpose, we developed MATAR, a C++ software library that allows for simple creation and use of intricate data structures that is also portable across disparate architectures using Kokkos. Here, the performance aspect is achieved by forcing contiguous memory layout (or as close to contiguous as possible) for multidimensional and multi-size dense or sparse MATrix and ARray (hence, MATAR) types. Our results show that MATAR has the capability to improve memory utilization, performance, and programmer productivity in scientific computing. This is achieved by fitting more work into the available memory, minimizing memory loads required, and by loading memory in the most efficient order. This document describes the purpose of the work, the implementation of each of the data types, and the resulting performance both in some simple baseline test cases and in an application code.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2025

Architecture-Aware Models of AI Engines for High-Performance Matrix Matrix Multiplication

The AI Engine (AIE) architecture, available in systems from mobile SoCs to server-class FPGAs, aims to efficiently execute AI/ML tasks through a two-dimensional array of compute tiles. Previous work on AIEs has explored different approaches to mapping computation across spatial arrays, but the compute kernel running on each tile has not been the focus. Additionally, the AIE-ML architecture introduces memory tiles and omits programmable logic, requiring new approaches to staging and moving data throughout the array. In this work we update analytical models developed for CPUs to produce the design of high performance kernels while introducing new model considerations such as memory structure, throughput, and latency as required by the AIE hardware. We evaluate our models by developing AIE-ML kernels for matrix multiplication in low-precision data types showing performance up to 95% of compute peak for the kernel when data resides in local memory and above 90% of compute peak when data resides in main memory.

Binder, Elliott D. [Carnegie Mellon University, Pi↗
NASA NTRS2010

Radiation-Hardened Solid-State Drive

A method is provided for a radiationhardened (rad-hard) solid-state drive for space mission memory applications by combining rad-hard and commercial off-the-shelf (COTS) non-volatile memories (NVMs) into a hybrid architecture. The architecture is controlled by a rad-hard ASIC (application specific integrated circuit) or a FPGA (field programmable gate array). Specific error handling and data management protocols are developed for use in a rad-hard environment. The rad-hard memories are smaller in overall memory density, but are used to control and manage radiation-induced errors in the main, and much larger density, non-rad-hard COTS memory devices. Small amounts of rad-hard memory are used as error buffers and temporary caches for radiation-induced errors in the large COTS memories. The rad-hard ASIC/FPGA implements a variety of error-handling protocols to manage these radiation-induced errors. The large COTS memory is triplicated for protection, and CRC-based counters are calculated for sub-areas in each COTS NVM array. These counters are stored in the rad-hard non-volatile memory. Through monitoring, rewriting, regeneration, triplication, and long-term storage, radiation-induced errors in the large NV memory are managed. The rad-hard ASIC/FPGA also interfaces with the external computer buses.

Sheldon, Douglas J.↗
NASA NTRS2007

High-Performance, Radiation-Hardened Electronics for Space Environments

The Radiation Hardened Electronics for Space Environments (RHESE) project endeavors to advance the current state-of-the-art in high-performance, radiation-hardened electronics and processors, ensuring successful performance of space systems required to operate within extreme radiation and temperature environments. Because RHESE is a project within the Exploration Technology Development Program (ETDP), RHESE's primary customers will be the human and robotic missions being developed by NASA's Exploration Systems Mission Directorate (ESMD) in partial fulfillment of the Vision for Space Exploration. Benefits are also anticipated for NASA's science missions to planetary and deep-space destinations. As a technology development effort, RHESE provides a broad-scoped, full spectrum of approaches to environmentally harden space electronics, including new materials, advanced design processes, reconfigurable hardware techniques, and software modeling of the radiation environment. The RHESE sub-project tasks are: SelfReconfigurable Electronics for Extreme Environments, Radiation Effects Predictive Modeling, Radiation Hardened Memory, Single Event Effects (SEE) Immune Reconfigurable Field Programmable Gate Array (FPGA) (SIRF), Radiation Hardening by Software, Radiation Hardened High Performance Processors (HPP), Reconfigurable Computing, Low Temperature Tolerant MEMS by Design, and Silicon-Germanium (SiGe) Integrated Electronics for Extreme Environments. These nine sub-project tasks are managed by technical leads as located across five different NASA field centers, including Ames Research Center, Goddard Space Flight Center, the Jet Propulsion Laboratory, Langley Research Center, and Marshall Space Flight Center. The overall RHESE integrated project management responsibility resides with NASA's Marshall Space Flight Center (MSFC). Initial technology development emphasis within RHESE focuses on the hardening of Field Programmable Gate Arrays (FPGA)s and Field Programmable Analog Arrays (FPAA)s for use in reconfigurable architectures. As these component/chip level technologies mature, the RHESE project emphasis shifts to focus on efforts encompassing total processor hardening techniques and board-level electronic reconfiguration techniques featuring spare and interface modularity. This phased approach to distributing emphasis between technology developments provides hardened FPGA/FPAAs for early mission infusion, then migrates to hardened, board-level, high speed processors with associated memory elements and high density storage for the longer duration missions encountered for Lunar Outpost and Mars Exploration occurring later in the Constellation schedule.

Keys, Andrew S.↗