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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 199 records · Page 11
All sourcesNASA NTRSDOE OSTI
NASA NTRS1986

HYTESS 2: A Hypothetical Turbofan Engine Simplified Simulation with multivariable control and sensor analytical redundancy

A hypothetical turbofan engine simplified simulation with a multivariable control and sensor failure detection, isolation, and accommodation logic (HYTESS II) is presented. The digital program, written in FORTRAN, is self-contained, efficient, realistic and easily used. Simulated engine dynamics were developed from linearized operating point models. However, essential nonlinear effects are retained. The simulation is representative of the hypothetical, low bypass ratio turbofan engine with an advanced control and failure detection logic. Included is a description of the engine dynamics, the control algorithm, and the sensor failure detection logic. Details of the simulation including block diagrams, variable descriptions, common block definitions, subroutine descriptions, and input requirements are given. Example simulation results are also presented.

Merrill, W. C.↗
NASA NTRS1973

Apollo experience report: Guidance and control systems - Digital autopilot design development

The development of the Apollo digital autopilots (the primary attitude control systems that were used for all phases of the lunar landing mission) is summarized. This report includes design requirements, design constraints, and design philosophy. The development-process functions and the essential information flow paths are identified. Specific problem areas that existed during the development are included. A discussion is also presented on the benefits inherent in mechanizing attitude-controller logic and dynamic compensation in a digital computer.

Peters, W. H.↗
NASA NTRS2009

"Glitch Logic" and Applications to Computing and Information Security

This paper introduces a new method of information processing in digital systems, and discusses its potential benefits to computing and information security. The new method exploits glitches caused by delays in logic circuits for carrying and processing information. Glitch processing is hidden to conventional logic analyses and undetectable by traditional reverse engineering techniques. It enables the creation of new logic design methods that allow for an additional controllable "glitch logic" processing layer embedded into a conventional synchronous digital circuits as a hidden/covert information flow channel. The combination of synchronous logic with specific glitch logic design acting as an additional computing channel reduces the number of equivalent logic designs resulting from synthesis, thus implicitly reducing the possibility of modification and/or tampering with the design. The hidden information channel produced by the glitch logic can be used: 1) for covert computing/communication, 2) to prevent reverse engineering, tampering, and alteration of design, and 3) to act as a channel for information infiltration/exfiltration and propagation of viruses/spyware/Trojan horses.

hardware vulnerabilities↗
NASA NTRS2007

My Rewarding Summer Research Experience at NASA

My summer research experience at the Kennedy Space Center has been a truly rewarding one. As an electrical engineering student at the University of South Florida, I was blessed with a beneficial opportunity to gain valuable knowledge in my career, and also apply it through working at NASA. One of my inspirations in becoming an engineer is to work at NASA someday, and I was very excited and honored to have this opportunity. My goal in this internship was to strengthen my preparation in becoming an engineer by learning new material, acquiring skills by practicing what I learned, and discovering the expectations of engineering work at NASA. Through this summer research, I was able to learn new computer programs and perform various tasks that gave me experience and skills as an engineer. My primary job was to conduct work on the Constellation Test article, which is a simulation model of the Crew Launch Vehicle (CLV) tanking system. This is a prototype of a launch facility and an Ares I Vehicle, which God willing will transport astronauts to the moon. Construction of the CLV is in progress and a test launch is anticipated for 2010. Moreover, the Test Article serves as a demonstration too, training test bed, and may be expanded for new simulation of launch system elements, which could be applied to real life operations. The test article is operated and run by a Programmable Logic Controller (PLC), which is a digital computer that is used to control all forms of machinery such as those in manufacturing buildings and other industries. PLCs are different than other computers because of the physical protection they have against damaging environmental conditions that would destroy other computers. Also, PLCs are equipped with lots of input and output connections that allow extensive amounts of commands to be executed, which would normally require many computers to do. Therefore, PLCs are small, rugged, and extremely powerful tools that may continue to be employed at NASA. Furthermore, in order to conduct productive work on the Test Article, I needed to learn the computer program called RS Logics 5000.

Aviles, Andres↗
NASA NTRS2009

Economical Implementation of a Filter Engine in an FPGA

A logic design has been conceived for a field-programmable gate array (FPGA) that would implement a complex system of multiple digital state-space filters. The main innovative aspect of this design lies in providing for reuse of parts of the FPGA hardware to perform different parts of the filter computations at different times, in such a manner as to enable the timely performance of all required computations in the face of limitations on available FPGA hardware resources. The implementation of the digital state-space filter involves matrix vector multiplications, which, in the absence of the present innovation, would ordinarily necessitate some multiplexing of vector elements and/or routing of data flows along multiple paths. The design concept calls for implementing vector registers as shift registers to simplify operand access to multipliers and accumulators, obviating both multiplexing and routing of data along multiple paths. Each vector register would be reused for different parts of a calculation. Outputs would always be drawn from the same register, and inputs would always be loaded into the same register. A simple state machine would control each filter. The output of a given filter would be passed to the next filter, accompanied by a "valid" signal, which would start the state machine of the next filter. Multiple filter modules would share a multiplication/accumulation arithmetic unit. The filter computations would be timed by use of a clock having a frequency high enough, relative to the input and output data rate, to provide enough cycles for matrix and vector arithmetic operations. This design concept could prove beneficial in numerous applications in which digital filters are used and/or vectors are multiplied by coefficient matrices. Examples of such applications include general signal processing, filtering of signals in control systems, processing of geophysical measurements, and medical imaging. For these and other applications, it could be advantageous to combine compact FPGA digital filter implementations with other application-specific logic implementations on single integrated-circuit chips. An FPGA could readily be tailored to implement a variety of filters because the filter coefficients would be loaded into memory at startup.

Kowalski, James E.↗
NASA NTRS1979

Procedure for extraction of disparate data from maps into computerized data bases

A procedure is presented for extracting disparate sources of data from geographic maps and for the conversion of these data into a suitable format for processing on a computer-oriented information system. Several graphic digitizing considerations are included and related to the NASA Earth Resources Laboratory's Digitizer System. Current operating procedures for the Digitizer System are given in a simplified and logical manner. The report serves as a guide to those organizations interested in converting map-based data by using a comparable map digitizing system.

Junkin, B. G.↗
DOE OSTI2025

Introduction: Neuromorphic Materials

The explosive growth in data collection and the need to process it efficiently, as well as the desire to automate increasingly complex tasks in transportation, medical care, manufacturing, security and many other fields have motivated a growing interest in neuromorphic computing. Unlike the binary, transistorbased ON/OFF logic gates and separate logic and memory functionalities employed in digital computing, neuromorphic computing is inspired by animal brains that use interconnected synapses and neurons to perform processing, storage and transmission of information at the same location, while only consuming ~20 W or less of power. Motivated by the brain’s efficiency, adaptability, self-learning and resiliency qualities, neuromorphic computing can be broadly defined as an approach to processing and storing information using hardware and algorithms inspired by models of biological neural systems. Present research in neuromorphic computing encompasses approaches that vary significantly in their degree of neuro-inspiration, from systems that only incorporate features such as asynchronous, event-driven operation or use crossbar arrays of non-volatile memory (NVM) elements to accelerate deep neural networks (DNNs), to designs that embrace the extreme parallelism, sparsity, reconfigurability, adaptability, complexity and stochasticity observed in nervous systems. The term ‘neuromorphic’ computing is often credited to Carver Mead, who in the 1980s investigated Si-based analog electronics to replicate functions of the animal retina. Earlier important advances in this field include the work of Frank Rosenblatt, who proposed the concept of the perceptron, Bernard Widrow, who used this concept to build one of the first analog neural networks, the Adaline and many other researchers (see ref. 6 for an historical perspective on neuromorphic computing). With the recent increase in the use of artificial intelligence and large language models, and rising concerns over the associated energy costs, interest in neuromorphic hardware has expanded rapidly. According to some estimates, driven largely by the drastic growth in the training use of artificial intelligence (AI) models using the current computing architectures, the energy cost of computing is projected to reach the energy supply worldwide by 2045. Furthermore, while this is not a realistic outcome, it means that, if more efficient computing technologies are not developed -- soon -- the world will soon become one where demand for energy and market constraints limit the continued increase of societal access to AI and cloud services from data centers. Data centers used for training and use of these models consume hundreds of terawatt hours of electricity, already past 4% of the US electricity demand.

Circuits↗
DOE OSTI2024

The SparkPix-S ASIC for the sparsified readout of 1 MHz frame-rate X-ray cameras at LCLS-II: pixel design and simulation results

Exploiting the “sparse” nature of the information in XPCS (X-ray Photon Correlation Spectroscopy) and XSVS (Speckle Visibility Spectroscopy) experiments, we present the SparkPix-S, a 3-sides buttable Application Specific Integrated Circuit (ASIC) based on a sparsified readout strategy for large-format hybrid detectors. The SparkPix-S architecture, based on the successful ePix family, will be composed as follows: a front-end 2-D matrix of 384×352 square pixels with 50 µm pitch is arranged to match the dimensions of a PIN Si-sensor matrix; charge readout, signal shaping and amplitude discrimination is performed at pixel-level, by means of a low-power (<18 µW) analog processor, which, in case of an event, negotiates access to an analog bus placed every other column; on the chip periphery (balcony), the information on each bus is digitized by an array of successive approximation analog-to-digital converters (SAR-ADCs) running at 10 Msps; on the digital back-end the global logic will generate the output data stream using low-voltage differential signalling (LVDS). A first prototype of the SparkPix-S, with a reduced matrix size of 96×96 pixels, is currently under production on a 130 nm CMOS technology. Simulated performance results show an equivalent noise charge <60 el. r.m.s. at 1 MHz repetition rate, with a maximum input energy of 60 keV and capability to discriminate charge signals with equivalent energy as low as 900 eV.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS1971

Design, development, fabrication and delivery of register and multiplexer units

Two complementary MOS monolithic chip types were developed, which contain a register and multiplexer unit to be used in the central processing unit of a digital computer. The partition of the logic into a chip size consistent with the characteristics of the packages is discussed. The logic was implemented by specially configured circuitry designed to layout, as well as to optimize, performance by taking advantage of the properties of CMOS logic. Of several approaches considered for generating LSI CMOS arrays, the CMOS standard cell array design technique was selected. These design automation techniques were used to generate the chip layout, art work and working master plates, followed by the fabrication and testing of the two chip types. Sixty functional LSI arrays were delivered.

Feller, A.↗
NASA NTRS1973

Some questions of an optimum probability synthesis of dynamic metalworking machine systems

Attempts were made to develop a dynamic metal working machine tool system using probability information on external factors and independent disturbances of the parameters. The problem was optimized in two stages: (1) creation of mathematical models under conditions determined by input influences, and (2) processing the results of calculations obtained on such models. Data were obtained on the patterns of distribution of dynamic quality characteristics of the tool, vibration frequencies and amplitudes, attenuation coefficients, and duration of a transition process. These data were obtained using a digital computer, statistical test methods, or logical possibility trees.

Dobrynin, S. A.↗
NASA NTRS1979

Simple digital pulse-programing circuit

Pulse-sequencing circuit uses only shift register and Exclusive-OR gates. Circuit also serves as date-transition edge detector (for rising or falling edges). It is used in sample-and-hold, analog-to-digital conversion sequence control, multiphase clock logic, precise delay control computer control logic, edge detectors, other timing applications, and provides simple means to generate timing and control signals for data transfer, addressing, or mode control in microprocessors and minicomputers.

Langston, J. L.↗
NASA NTRS1981

Microchannel spatial light modulator

The Microchannel Spatial Light Modulator (MSLM), a versatile, highly sensitive, and optically addressed device being developed for real time optical information processing is discussed. The MSLM operates by converting an input optical image into a charge distribution at the surface of an electro-optic crystal. The charge distribution generates an electric field which modulates the refractive index of the crystal and thereby the phase or intensity of an image readout beam. Prototype devices employing 250 micron thick crystals exhibited a spatial resolution of 5 cycles/mm at 50% contrast, an exposure sensitivity of 2.2 nJ/cu cm and framing rates of 40 Hz with full modulation depth. The image processing operations that have been achieved using the internal processing mode of the MSLM include contrast reversal, contrast enhancement, edge enhancement, image addition and subtraction, analog and digital intensity thresholding, and binary level logic operations such as AND, OR, EXCLUSIVE OR, and NOR.

Warde, C.↗
NASA NTRS1993

Testing of the on-board attitude determination and control algorithms for SAMPEX

Algorithms for on-board attitude determination and control of the Solar, Anomalous, and Magnetospheric Particle Explorer (SAMPEX) have been expanded to include a constant gain Kalman filter for the spacecraft angular momentum, pulse width modulation for the reaction wheel command, an algorithm to avoid pointing the Heavy Ion Large Telescope (HILT) instrument boresight along the spacecraft velocity vector, and the addition of digital sun sensor (DSS) failure detection logic. These improved algorithms were tested in a closed-loop environment for three orbit geometries, one with the sun perpendicular to the orbit plane, and two with the sun near the orbit plane - at Autumnal Equinox and at Winter Solstice. The closed-loop simulator was enhanced and used as a truth model for the control systems' performance evaluation and sensor/actuator contingency analysis. The simulations were performed on a VAX 8830 using a prototype version of the on-board software.

Mccullough, Jon D.↗
NASA NTRS1976

Two-dimensional radiant energy array computers and computing devices

Two dimensional digital computers and computer devices operate in parallel on rectangular arrays of digital radiant energy optical signal elements which are arranged in ordered rows and columns. Logic gate devices receive two input arrays and provide an output array having digital states dependent only on the digital states of the signal elements of the two input arrays at corresponding row and column positions. The logic devices include an array of photoconductors responsive to at least one of the input arrays for either selectively accelerating electrons to a phosphor output surface, applying potentials to an electroluminescent output layer, exciting an array of discrete radiant energy sources, or exciting a liquid crystal to influence crystal transparency or reflectivity.

Schaefer, D. H.↗
NASA NTRS2000

Digital Channel Simulator Developed and Tested

The Digital Channel Simulator (DCS) is a real-time test set developed in-house by the NASA Glenn Research Center at Lewis Field that simulates the characteristics of the modulator, demodulator, and transmission medium in a typical communications system to enable controlled laboratory testing of codec pairs. The DCS can support data rates up to 100 megasymbols per second (Msymbols/sec) with symbol sizes up to 10 bits and is compatible with both TTL (transistor transistor logic) and ECL (emitter coupled logic) interfaces. Because of its use of digital integrated circuits (IC's), the DCS offers the user accurate and repeatable testing while maintaining a simple reconfiguration of the modulation scheme and noise characteristics. The PC-based graphical user interface (GUI) assures user friendly operation for configuring, controlling, and monitoring the DCS and system during tests. In a typical communications system, the modulator places a symbol in constellation space and puts it on a carrier to be sent to the demodulator. Because of noise on the channel, the I and Q position in constellation space cannot be recovered exactly, and the received coordinates shift. To mimic this process in the laboratory, the DCS uses a mapper to place the symbol in constellation space. It simulates the shift in coordinates by digitally adding "noise" to the I and Q values. The mapper and noise source are implemented in lookup tables. Modulation schemes and noise characteristics are set by the values loaded in these tables. The mapper also has a pass-through mode to facilitate modulator testing, allowing noise to be added to 8-bit I and Q values of modulated data without a second mapping. To achieve high symbol rates, eight processing circuits are placed in parallel between an ECL demultiplexer and multiplexer. A graphical user interface was developed to calculate, load, and verify the values for the lookup tables. This interface can also be used to debug and verify proper operation of the channel simulator or to control an experiment. Operation of the DCS has been verified through three tests: a low-speed comprehensive system test, a high-speed (20 Msymbols/sec) test of the TTL interface, and a high-speed (100 Msymbols/sec) test of the ECL interface. The DCS is now ready for use by NASA and external customers.

Bizon, Thomas P.↗
NASA NTRS1981

Flight test of a full authority Digital Electronic Engine Control system in an F-15 aircraft

The Digital Electronic Engine Control (DEEC) system considered is a relatively low cost digital full authority control system containing selectively redundant components and fault detection logic with capability for accommodating faults to various levels of operational capability. The DEEC digital control system is built around a 16-bit, 1.2 microsecond cycle time, CMOS microprocessor, microcomputer system with approximately 14 K of available memory. Attention is given to the control mode, component bench testing, closed loop bench testing, a failure mode and effects analysis, sea-level engine testing, simulated altitude engine testing, flight testing, the data system, cockpit, and real time display.

Barrett, W. J.↗