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At least 199 records · Page 11

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NASA NTRS2001

A Step Response Based Mixed-Signal BIST Approach

A new Mixed-Signal Built-in Self-test approach that is based upon the step response of a reconfigurable (or multifunction) analog block is presented in this paper. The technique requires the overlapping step response of the Circuit Under Test (CUT) for two circuit configurations. Each configuration can be realized by changing the topology of the CUT or by sampling two CUT nodes with differing step responses. The technique can effectively detect both soft and hard faults and does not require an analog-to-digital converter (ADC) and/or digital-to-analog converter( DAC). It also does not require any precision voltage sources or comparators. The approach does not require any additional analog circuits to realize the test signal generator and a two input analog multiplexer for CUT test node sampling. The paper is concluded with the application of the proposed approach to a circuit found in the work of Epstein et a1 and two ITC 97 analog benchmark circuits.

Walker, Alvernon↗

NASA NTRS1974

Life support subsystem monitoring instrumentation

The recognition of the need for instrumentation in manned spacecraft life-support subsystems has increased significantly over the past several years. Of the required control and monitoring instrumentation, this paper will focus on the monitoring instrumentation as applied to life-support subsystems. The initial approach used independent sensors, independent sensor signal conditioning circuitry, and independent logic circuitry to provide shutdown protection only. This monitoring system was replaced with a coordinated series of printed circuit cards, each of which contains all the electronics to service one sensor and provide performance trend information, fault detection and isolation information, and shutdown protection. Finally, a review of sensor and instrumentation problems is presented, and the requirement for sensors with built-in signal conditioning and provisions for in situ calibration is discussed.

Powell, J. D.↗

NASA NTRS2011

Accelerated Aging with Electrical Overstress and Prognostics for Power MOSFETs

Power electronics play an increasingly important role in energy applications as part of their power converter circuits. Understanding the behavior of these devices, especially their failure modes as they age with nominal usage or sudden fault development is critical in ensuring efficiency. In this paper, a prognostics based health management of power MOSFETs undergoing accelerated aging through electrical overstress at the gate area is presented. Details of the accelerated aging methodology, modeling of the degradation process of the device and prognostics algorithm for prediction of the future state of health of the device are presented. Experiments with multiple devices demonstrate the performance of the model and the prognostics algorithm as well as the scope of application. Index Terms Power MOSFET, accelerated aging, prognostics

Saha, Sankalita↗

NASA NTRS1985

Study of Contact Resistances in Integrated Circuits

Techniques explored in search for rapid, reliable test. Resistances of aluminum/silicon contacts and methods to measure subjects of NASA report. Study with three tasks undertaken to evaluate nature and reliability of large numbers of semiconductor contacts of type now being fabricated in integrated circuits: Develop yield analysis for series strings of contacts using wafer-level electrical measurements, and identify different types of faults by visual inspection; develop wafer-level tests to evaluate reliability of contact strings; and develop mathematical model for current flow in contacts and examine contact region for evidence of micro-alloying.

Buehler, M. G.↗

NASA NTRS2009

Lithium Ion Battery (LIB) Charger: Spacesuit Battery Charger Design with 2-Fault Tolerance to Catastrophic Hazards

Charger design that is 2-fault tolerant to catastrophic has been achieved for the Spacesuit Li-ion Battery with key features. Power supply control circuit and 2 microprocessors independently control against overcharge. 3 microprocessor control against undercharge (false positive: Go for EVA) conditions. 2 independent channels provide functional redundancy. Capable of charge balancing cell banks in series. Cell manufacturing and performance uniformity is excellent with both designs. Once a few outliers are removed, LV cells are slightly more uniform than MoliJ cells. If cell balance feature of charger is ever invoked, it will be an indication of a significant degradation issue, not a nominal condition.

Darcy, Eric↗

NASA NTRS2015

Architecture, Voltage, and Components for a Turboelectric Distributed Propulsion Electric Grid

The development of a wholly superconducting turboelectric distributed propulsion system presents unique opportunities for the aerospace industry. However, this transition from normally conducting systems to superconducting systems significantly increases the equipment complexity necessary to manage the electrical power systems. Due to the low technology readiness level (TRL) nature of all components and systems, current Turboelectric Distributed Propulsion (TeDP) technology developments are driven by an ambiguous set of system-level electrical integration standards for an airborne microgrid system (Figure 1). While multiple decades' worth of advancements are still required for concept realization, current system-level studies are necessary to focus the technology development, target specific technological shortcomings, and enable accurate prediction of concept feasibility and viability. An understanding of the performance sensitivity to operating voltages and an early definition of advantageous voltage regulation standards for unconventional airborne microgrids will allow for more accurate targeting of technology development. Propulsive power-rated microgrid systems necessitate the introduction of new aircraft distribution system voltage standards. All protection, distribution, control, power conversion, generation, and cryocooling equipment are affected by voltage regulation standards. Information on the desired operating voltage and voltage regulation is required to determine nominal and maximum currents for sizing distribution and fault isolation equipment, developing machine topologies and machine controls, and the physical attributes of all component shielding and insulation. Voltage impacts many components and system performance.

electric faults↗

NASA NTRS2002

Fly-By-Light/Power-By-Wire Fault-Tolerant Fiber-Optic Backplane

The design and development of a fault-tolerant fiber-optic backplane to demonstrate feasibility of such architecture is presented. The simulation results of test cases on the backplane in the advent of induced faults are presented, and the fault recovery capability of the architecture is demonstrated. The architecture was designed, developed, and implemented using the Very High Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL). The architecture was synthesized and implemented in hardware using Field Programmable Gate Arrays (FPGA) on multiple prototype boards.

Malekpour, Mahyar R.↗

NASA NTRS2002

Validation of an SEU simulation technique for a complex processor: PowerPC7400

Published data on the processors sensitivites with respect to SEU is generally obtained from radiation ground testing during which the program is executed by the DUT consists in the sequential inspection of each of the processor memory cells accessible to the user, through the execution of a suitable instruction sequence. In such programs, so-called static tests, typically considered memory cells are general-purpose registers, special registers (program counter, stack pointer...) and internal memory. Nevertheless, the register use and duty cycle of the final application will be very different, including using instructions no in the static tests and disturbing other potential SEU targets. The ideal would be the use of the final application program for the radiation ground testing, but generally this program is either unknown or unavailable when the qualification testing is performed on candidate circuits to space projects.

Radiation↗

NASA NTRS1988

Development of a space-systems network testbed

This paper describes a communications network testbed which has been designed to allow the development of architectures and algorithms that meet the functional requirements of future NASA communication systems. The central hardware components of the Network Testbed are programmable circuit switching communication nodes which can be adapted by software or firmware changes to customize the testbed to particular architectures and algorithms. Fault detection, isolation, and reconfiguration has been implemented in the Network with a hybrid approach which utilizes features of both centralized and distributed techniques to provide efficient handling of faults within the Network.

Lala, Jaynarayan↗

NASA NTRS1989

Electrical performance characteristics of high power converters for space power applications

The first goal of this project was to investigate various converters that would be suitable for processing electric power derived from a nuclear reactor. The implementation is indicated of a 20 kHz system that includes a source converter, a ballast converter, and a fixed frequency converter for generating the 20 kHz output. This system can be converted to dc simply by removing the fixed frequency converter. This present study emphasized the design and testing of the source and ballast converters. A push-pull current-fed (PPCF) design was selected for the source converter, and a 2.7 kW version of this was implemented using three 900 watt modules in parallel. The characteristic equation for two converters in parallel was derived, but this analysis did not yield any experimental methods for measuring relative stability. The three source modules were first tested individually and then in parallel as a 2.7 kW system. All tests proved to be satisfactory; the system was stable; efficiency and regulation were acceptable; and the system was fault tolerant. The design of a ballast-load converter, which was operated as a shunt regulator, was investigated. The proposed power circuit is suitable for use with BJTs because proportional base drive is easily implemented. A control circuit which minimizes switching frequency ripple and automatically bypasses a faulty shunt section was developed. A nonlinear state-space-averaged model of the shunt regulator was developed and shown to produce an accurate incremental (small-signal) dynamic model, even though the usual state-space-averaging assumptions were not met. The nonlinear model was also shown to be useful for large-signal dynamic simulation using PSpice.

Stuart, Thomas A.↗

NASA NTRS1993

Destination-directed, packet-switched architecture for a geostationary communications satellite network

A major goal of the Digital Systems Technology Branch at the NASA Lewis Research Center is to identify and develop critical digital components and technologies that either enable new commercial missions or significantly enhance the performance, cost efficiency, and/or reliability of existing and planned space communications systems. NASA envisions a need for low-data-rate, interactive, direct-to-the-user communications services for data, voice, facsimile, and video conferencing. The network would provide enhanced very-small-aperture terminal (VSAT) communications services and be capable of handling data rates of 64 kbps through 2.048 Mbps in 64-kbps increments. Efforts have concentrated heavily on the space segment; however, the ground segment has been considered concurrently to ensure cost efficiency and realistic operational constraints. The focus of current space segment developments is a flexible, high-throughput, fault-tolerant onboard information-switching processor (ISP) for a geostationary satellite communications network. The Digital Systems Technology Branch is investigating both circuit and packet architectures for the ISP. Destination-directed, packet-switched architectures for geostationary communications satellites are addressed.

Ivancic, William D.↗

NASA NTRS2004

Fault tolerant state machines

Explore the source record for details and available documents.

state machines↗

NASA NTRS1989

REDEX: The ranging equipment diagnostic expert system

REDEX, an advanced prototype expert system that diagnoses hardware failures in the Ranging Equipment (RE) at NASA's Ground Network tracking stations is described. REDEX will help the RE technician identify faulty circuit cards or modules that must be replaced, and thereby reduce troubleshooting time. It features a highly graphical user interface that uses color block diagrams and layout diagrams to illustrate the location of a fault. A semantic network knowledge representation technique was used to model the design structure of the RE. A catalog of generic troubleshooting rules was compiled to represent heuristics that are applied in diagnosing electronic equipment. Specific troubleshooting rules were identified to represent additional diagnostic knowledge that is unique to the RE. Over 50 generic and 250 specific troubleshooting rules have been derived. REDEX is implemented in Prolog on an IBM PC AT-compatible workstation. Block diagram graphics displays are color-coded to identify signals that have been monitored or inferred to have nominal values, signals that are out of tolerance, and circuit cards and functions that are diagnosed as faulty. A hypertext-like scheme is used to allow the user to easily navigate through the space of diagrams and tables. Over 50 graphic and tabular displays have been implemented. REDEX is currently being evaluated in a stand-alone mode using simulated RE fault scenarios. It will soon be interfaced to the RE and tested in an online environment. When completed and fielded, REDEX will be a concrete example of the application of expert systems technology to the problem of improving performance and reducing the lifecycle costs of operating NASA's communications networks in the 1990's.

Luczak, Edward C.↗

NASA NTRS1989

REDEX - The ranging equipment diagnostic expert system

Luczak, Edward C.↗

NASA NTRS2018

A Blueprint for Demonstrating Quantum Supremacy with Superconducting Qubits

Long coherence times and high fidelity control recently achieved in scalable superconducting circuits paved the way for the growing number of experimental studies of many-qubit quantum coherent phenomena in these devices. Albeit full implementation of quantum error correction and fault tolerant quantum computation remains a challenge the near term pre-error correction devices could allow new fundamental experiments despite inevitable accumulation of errors. One such open question foundational for quantum computing is achieving the so called quantum supremacy, an experimental demonstration of a computational task that takes polynomial time on the quantum computer whereas the best classical algorithm would require exponential time and/or resources. It is possible to formulate such a task for a quantum computer consisting of less than a 100 qubits. The computational task we consider is to provide approximate samples from a non-trivial quantum distribution. This is a generalization for the case of superconducting circuits of ideas behind boson sampling protocol for quantum optics introduced by Arkhipov and Aaronson. In this presentation we discuss a proof-of-principle demonstration of such a sampling task on a 9-qubit chain of superconducting gmon qubits developed by Google. We discuss theoretical analysis of the driven evolution of the device resulting in output approximating samples from a uniform distribution in the Hilbert space, a quantum chaotic state. We analyze quantum chaotic characteristics of the output of the circuit and the time required to generate a sufficiently complex quantum distribution. We demonstrate that the classical simulation of the sampling output requires exponential resources by connecting the task of calculating the output amplitudes to the sign problem of the Quantum Monte Carlo method. We also discuss the detailed theoretical modeling required to achieve high fidelity control and calibration of the multi-qubit unitary evolution in the device. We use a novel cross-entropy statistical metric as a figure of merit to verify the output and calibrate the device controls. Finally, we demonstrate the statistics of the wave function amplitudes generated on the 9-gmon chain and verify the quantum chaotic nature of the generated quantum distribution. This verifies the implementation of the quantum supremacy protocol.

Kechedzhi, Kostyantyn↗

NASA NTRS2010

Flexible Peripheral Component Interconnect Input/Output Card

The Flexible Peripheral Component Interconnect (PCI) Input/Output (I/O) Card is an innovative circuit board that provides functionality to interface between a variety of devices. It supports user-defined interrupts for interface synchronization, tracks system faults and failures, and includes checksum and parity evaluation of interface data. The card supports up to 16 channels of high-speed, half-duplex, low-voltage digital signaling (LVDS) serial data, and can interface combinations of serial and parallel devices. Placement of a processor within the field programmable gate array (FPGA) controls an embedded application with links to host memory over its PCI bus. The FPGA also provides protocol stacking and quick digital signal processor (DSP) functions to improve host performance. Hardware timers, counters, state machines, and other glue logic support interface communications. The Flexible PCI I/O Card provides an interface for a variety of dissimilar computer systems, featuring direct memory access functionality. The card has the following attributes: 8/16/32-bit, 33-MHz PCI r2.2 compliance, Configurable for universal 3.3V/5V interface slots, PCI interface based on PLX Technology's PCI9056 ASIC, General-use 512K 16 SDRAM memory, General-use 1M 16 Flash memory, FPGA with 3K to 56K logical cells with embedded 27K to 198K bits RAM, I/O interface: 32-channel LVDS differential transceivers configured in eight, 4-bit banks; signaling rates to 200 MHz per channel, Common SCSI-3, 68-pin interface connector.

Bigelow, Kirk K.↗

NASA NTRS1991

Thermal verification testing of commercial printed-circuit boards for spaceflight

A method is discussed developed to verify commercial printed-circuit boards for a shuttle orbital flight. The Space Acceleration Measurement System Project used this method first with great success. The test sequence is based on early fault detection, desire to test the final assembly, and integration with other verification testing. A component thermal screening test is performed first to force flaws in design, workmanship, parts, processes, and materials into observable failures. Then temperature definition tests are performed that consist of infrared scanning, thermal vacuum testing, and preliminary thermal operational testing. Only the engineering unit is used for temperature definition testing, but the preliminary thermal operational testing is performed on the flight unit after the temperature range has been defined. In the sequence of testing, vibration testing is performed next, but most vibration failures cannot be detected without subsequent temperature cycling. Finally, final assembly testing is performed to simulate the shuttle flight. An abbreviated thermal screening test is performed as a check after the vibration test, and then a complete thermal operational test is performed. The final assembly test finishes up with a burn-in of 100 hours of trouble-free operation. Verification is successful when all components and final assemblies have passed each test satisfactory. This method was very successful in verifying that commercial printed-circuit boards will survive in the shuttle environment.

Foster, William M., II↗

NASA NTRS1993

Test pattern generation for ILA sequential circuits

An efficient method of generating test patterns for sequential machines implemented using one-dimensional, unilateral, iterative logic arrays (ILA's) of BTS pass transistor networks is presented. Based on a transistor level fault model, the method affords a unique opportunity for real-time fault detection with improved fault coverage. The resulting test sets are shown to be equivalent to those obtained using conventional gate level models, thus eliminating the need for additional test patterns. The proposed method advances the simplicity and ease of the test pattern generation for a special class of sequential circuitry.

Feng, YU↗