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At least 199 records · Page 11
All sourcesNASA NTRSDOE OSTI
NASA NTRS1998

Mineralization of Bacteria in Terrestrial Basaltic Rocks: Comparison With Possible Biogenic Features in Martian Meteorite Allan Hills 84001

The identification of biogenic features altered by diagenesis or mineralization is important in determining whether specific features in terrestrial rocks and in meteorites may have a biogenic origin. Unfortunately, few studies have addressed the formation of biogenic features in igneous rocks, which may be important to these phenomena, including the controversy over possible biogenic features in basaltic martian meteorite ALH84001. To explore the presence of biogenic features in igneous rocks, we examined microcosms growing in basaltic small-scale experimental growth chambers or microcosms. Microbial communities were harvested from aquifers of the Columbia River Basalt (CRB) group and grown in a microcosm containing unweathered basalt chips and groundwater (technique described in. These microcosms simulated natural growth conditions in the deep subsurface of the CRB, which should be a good terrestrial analog for any putative martian subsurface ecosystem that may have once included ALH84001. Here we present new size measurements and photomicrographs comparing the putative martian fossils to biogenic material in the CRB microcosms. The range of size and shapes of the biogenic features on the CRB microcosm chips overlaps with and is similar to those on ALH84001 chips. Although this present work does not provide evidence for the biogenicity of ALH84001 features, we believe that, based on criteria of size, shape, and general morphology, a biogenic interpretation for the ALH84001 features remains plausible.

Thomas-Keprta, K. L.↗
NASA NTRS2003

Nanotubes May Break Through "Chip Wall"

In 1965, just four years after the first planar integrated circuit (IC) was discovered, Cordon Moore observed that the number of transistors per integrated circuit had grown exponentially. He predicted that this would continue, and the media soon began to call his prophesy "Moore's Law" For nearly forty years, Moore's Law has been validated by the technological progress achieved in the semiconductor industry. Now, however, industry experts are warning of a "Red Brick Wall" that may soon block the continued scaling predicted by by Moore's Law. The "red bricks" in the wall are those areas of technical challenge for which no known manufacturable solution exists. One such "brick" is the challenge of finding a new material and processing technology to replace the metals used today to interconnect transistors on a chip.

Laufenberg, Larry↗
NASA NTRS2010

System on a Chip (SoC) Overview

System-on-a-chip or system on chip (SoC or SOC) refers to integrating all components of a computer or other electronic system into a single integrated circuit (chip). It may contain digital, analog, mixed-signal, and often radio-frequency functions all on a single chip substrate. Complexity drives it all: Radiation tolerance and testability are challenges for fault isolation, propagation, and validation. Bigger single silicon die than flown before and technology is scaling below 90nm (new qual methods). Packages have changed and are bigger and more difficult to inspect, test, and understand. Add in embedded passives. Material interfaces are more complex (underfills, processing). New rules for board layouts. Mechanical and thermal designs, etc.

LaBel, Kenneth A.↗
NASA NTRS2010

Biasable, Balanced, Fundamental Submillimeter Monolithic Membrane Mixer

This device is a biasable, submillimeter-wave, balanced mixer fabricated using JPL s monolithic membrane process a simplified version of planar membrane technology. The primary target application is instrumentation used for analysis of atmospheric constituents, pressure, temperature, winds, and other physical and chemical properties of the atmospheres of planets and comets. Other applications include high-sensitivity gas detection and analysis. This innovation uses a balanced configuration of two diodes allowing the radio frequency (RF) signal and local oscillator (LO) inputs to be separated. This removes the need for external diplexers that are inherently narrowband, bulky, and require mechanical tuning to change frequency. Additionally, this mixer uses DC bias-ability to improve its performance and versatility. In order to solve problems relating to circuit size, the GaAs membrane process was created. As much of the circuitry as possible is fabricated on-chip, making the circuit monolithic. The remainder of the circuitry is precision-machined into a waveguide block that holds the GaAs circuit. The most critical alignments are performed using micron-scale semiconductor technology, enabling wide bandwidth and high operating frequencies. The balanced mixer gets superior performance with less than 2 mW of LO power. This can be provided by a simple two-stage multiplier chain following an amplifier at around 90 GHz. Further, the diodes are arranged so that they can be biased. Biasing pushes the diodes closer to their switching voltage, so that less LO power is required to switch the diodes on and off. In the photo, the diodes are at the right end of the circuit. The LO comes from the waveguide at the right into a reduced-height section containing the diodes. Because the diodes are in series to the LO signal, they are both turned on and off simultaneously once per LO cycle. Conversely, the RF signal is picked up from the RF waveguide by the probe at the left, and flows rightward to the diodes. Because the RF is in a quasi- TEM (suspended, microstrip-like) mode, it impinges on the diodes in an anti-parallel mode that does not couple to the waveguide mode. This isolates the LO and RF signals. This operation is similar to a cross-bar mixer used at low frequencies, except the RF signal enters through the back-short end of the waveguide rather than through the side. The RF probe also conveys the down-converted intermediate frequency (IF) signal out to an off-chip circuit board through a simple LC low-pass filter to the left as indicated. The bias is brought to the diodes through a bypass capacitor at the top.

Siegel, Peter↗
NASA NTRS2006

Robust Bioinformatics Recognition with VLSI Biochip Microsystem

A microsystem architecture for real-time, on-site, robust bioinformatic patterns recognition and analysis has been proposed. This system is compatible with on-chip DNA analysis means such as polymerase chain reaction (PCR)amplification. A corresponding novel artificial neural network (ANN) learning algorithm using new sigmoid-logarithmic transfer function based on error backpropagation (EBP) algorithm is invented. Our results show the trained new ANN can recognize low fluorescence patterns better than the conventional sigmoidal ANN does. A differential logarithmic imaging chip is designed for calculating logarithm of relative intensities of fluorescence signals. The single-rail logarithmic circuit and a prototype ANN chip are designed, fabricated and characterized.

bioinformatics↗
NASA NTRS1987

Parallel VLSI architecture emulation and the organization of APSA/MPP

The Applicative Programming System Architecture (APSA) combines an applicative language interpreter with a novel parallel computer architecture that is well suited for Very Large Scale Integration (VLSI) implementation. The Massively Parallel Processor (MPP) can simulate VLSI circuits by allocating one processing element in its square array to an area on a square VLSI chip. As long as there are not too many long data paths, the MPP can simulate a VLSI clock cycle very rapidly. The APSA circuit contains a binary tree with a few long paths and many short ones. A skewed H-tree layout allows every processing element to simulate a leaf cell and up to four tree nodes, with no loss in parallelism. Emulation of a key APSA algorithm on the MPP resulted in performance 16,000 times faster than a Vax. This speed will make it possible for the APSA language interpreter to run fast enough to support research in parallel list processing algorithms.

Odonnell, John T.↗
NASA NTRS1991

Low cost high efficiency GaAs monolithic RF module for SARSAT distress beacons

Low cost high performance (5 Watts output) 406 MHz beacons are urgently needed to realize the maximum utilization of the Search and Rescue Satellite-Aided Tracking (SARSAT) system spearheaded in the U.S. by NASA. Although current technology can produce beacons meeting the output power requirement, power consumption is high due to the low efficiency of available transmitters. Field performance is currently unsatisfactory due to the lack of safe and reliable high density batteries capable of operation at -40 C. Low cost production is also a crucial but elusive requirement for the ultimate wide scale utilization of this system. Microwave Monolithics Incorporated (MMInc.) has proposed to make both the technical and cost goals for the SARSAT beacon attainable by developing a monolithic GaAs chip set for the RF module. This chip set consists of a high efficiency power amplifier and a bi-phase modulator. In addition to implementing the RF module in Monolithic Microwave Integrated Circuit (MMIC) form to minimize ultimate production costs, the power amplifier has a power-added efficiency nearly twice that attained with current commercial technology. A distress beacon built using this RF module chip set will be significantly smaller in size and lighter in weight due to a smaller battery requirement, since the 406 MHz signal source and the digital controller have far lower power consumption compared to the 5 watt power amplifier. All the program tasks have been successfully completed. The GaAs MMIC RF module chip set has been designed to be compatible with the present 406 MHz signal source and digital controller. A complete high performance low cost SARSAT beacon can be realized with only additional minor iteration and systems integration.

Petersen, W. C.↗
NASA NTRS1985

The VLSI design of error-trellis syndrome decoding for convolutional codes

A recursive algorithm using the error-trellis decoding technique is developed to decode convolutional codes (CCs). An example, illustrating the very large scale integration (VLSI) architecture of such a decode, is given for a dual-K CC. It is demonstrated that such a decoder can be realized readily on a single chip with metal-nitride-oxide-semiconductor technology.

Reed, I. S.↗
NASA NTRS1986

The VLSI design of an error-trellis syndrome decoder for certain convolutional codes

A recursive algorithm using the error-trellis decoding technique is developed to decode convolutional codes (CCs). An example, illustrating the very large scale integration (VLSI) architecture of such a decode, is given for a dual-K CC. It is demonstrated that such a decoder can be realized readily on a single chip with metal-nitride-oxide-semiconductor technology.

Reed, I. S.↗
NASA NTRS1991

NASA Space Engineering Research Center for VLSI systems design

This annual review reports the center's activities and findings on very large scale integration (VLSI) systems design for 1990, including project status, financial support, publications, the NASA Space Engineering Research Center (SERC) Symposium on VLSI Design, research results, and outreach programs. Processor chips completed or under development are listed. Research results summarized include a design technique to harden complementary metal oxide semiconductors (CMOS) memory circuits against single event upset (SEU); improved circuit design procedures; and advances in computer aided design (CAD), communications, computer architectures, and reliability design. Also described is a high school teacher program that exposes teachers to the fundamentals of digital logic design.

Source record↗
NASA NTRS2014

Study of a Flexible Low Profile Tunable Dipole Antenna Using Barium Strontium Titanate Varactors

In this paper a flexible low profile dipole antenna using a frequency selective surface (FSS) with interdigital barium strontium titanate (BST) varactor-tuned unit cells is presented. The varactor chips were placed only along one dimension of the FSS to avoid the use of vias and simplify the DC bias network. The antenna uses overlapping metallic plates that resemble fish scales as a ground plane to improve the flexibility of the multi-material stack structure. The measured data of the antenna demonstrate tunability from 2.42 GHz to 2.66 GHz and 1.3 dB gain drop when using overlapping metallic plates instead of continuous ground plane. The total antenna thickness is approximately lambda/24.

Flexible antennas↗
NASA NTRS1997

A Thermal and Electrical Analysis of Power Semiconductor Devices

The state-of-art power semiconductor devices require a thorough understanding of the thermal behavior for these devices. Traditional thermal analysis have (1) failed to account for the thermo-electrical interaction which is significant for power semiconductor devices operating at high temperature, and (2) failed to account for the thermal interactions among all the levels involved in, from the entire device to the gate micro-structure. Furthermore there is a lack of quantitative studies of the thermal breakdown phenomenon which is one of the major failure mechanisms for power electronics. This research work is directed towards addressing. Using a coupled thermal and electrical simulation, in which the drift-diffusion equations for the semiconductor and the energy equation for temperature are solved simultaneously, the thermo-electrical interactions at the micron scale of various junction structures are thoroughly investigated. The optimization of gate structure designs and doping designs is then addressed. An iterative numerical procedure which incorporates the thermal analysis at the device, chip and junction levels of the power device is proposed for the first time and utilized in a BJT power semiconductor device. In this procedure, interactions of different levels are fully considered. The thermal stability issue is studied both analytically and numerically in this research work in order to understand the mechanism for thermal breakdown.

Vafai, Kambiz↗
NASA NTRS2001

Miniature Free-Flying Magnetometer Utilizing System-On-A-Chip Technology

Four Free-Flying Magnetometers (FFMs), developed at the Jet Propulsion Laboratory (JPL) for the Enstrophy mission, were successfully deployed from the payload of a sounding rocket launched from Poker Flats, Alaska on February 11, 1999. The FFMs functioned successfully by synchronously measuring the vector magnetic field at 4 points separate from the payload and at relative distances up to 3 km, and communicated their data, in bursts, to the ground. This is the first time synchronized in-situ multipoint measurements of the Earth's magnetic field utilizing miniature spin-stabilized "sensorcraft" have been performed. The data they provided have enabled, for the first time, the direct measure of field-aligned current density and are enabling new science by determining the fine-scale structure of the currents in the Earth's ionosphere involved in the production of aurora. These proof-of-concept "hockey puck" (80 mm diameter, 38 mm height, 250 gram mass) FFMs were built using off-the-shelf commercial, industrial, and military grade surface-mount electronic components. Radiation-hard electronics was not required for the Enstrophy mission's short sub-orbital flight. The successful design, implementation, and flight demonstration of this 1st generation FFM design has provided a solid base for further development of a 2nd generation FFM design for planetary science applications. A reliable ultra-miniature radiation-hard 2nd-generation FFM utilizing System-On-A-Chip (SOAC) technologies is proposed. This design would be targeted for long-term planetary missions to investigate magnetospheric field configurations in regions having small-scale structure and to separate spatial and temporal variations. A fleet of short-lived (expendable) FFMs would be deployed into a targeted region to gather multiprobe vector magnetic field data. The FFMs would be ejected from a parent spacecraft at a speed of a few m/sec and would cover spatial volumes of order tens of kilometers for times of order one hour. The parent spacecraft would carry a sufficient number of FFMs for multiple deployments. Additional information is contained in the original extended abstract.

Eyre, F. B.↗
NASA NTRS1972

Minimizing the area required for time constants in integrated circuits

When a medium- or large-scale integrated circuit is designed, efforts are usually made to avoid the use of resistor-capacitor time constant generators. The capacitor needed for this circuit usually takes up more surface area on the chip than several resistors and transistors. When the use of this network is unavoidable, the designer usually makes an effort to see that the choice of resistor and capacitor combinations is such that a minimum amount of surface area is consumed. The optimum ratio of resistance to capacitance that will result in this minimum area is equal to the ratio of resistance to capacitance which may be obtained from a unit of surface area for the particular process being used. The minimum area required is a function of the square root of the reciprocal of the products of the resistance and capacitance per unit area. This minimum occurs when the area required by the resistor is equal to the area required by the capacitor.

Lyons, J. C.↗
NASA NTRS1979

Spread spectrum techniques for the Space Shuttle

The Space Shuttle will employ spread spectrum techniques for both communication and navigation. During on-orbit phases of flight, two-way S-band and Ku-band communication links between the Shuttle and the ground will be available via the tracking and data relay satellite system (TDRSS). A pseudonoise (PN) code will spread the forward-link data spectrum from 32 kbps to 216 kbps to reduce the signal spectral density impinging on the earth's surface, with the S-band code search and acquisition being performed at C/NO-values of around 5 dB-Hz, and with a code length of 2047 chips at a rate of 11.232 Mchips/sec. C/NO-values in the region of 60 dB-Hz to 63 dB-Hz will characterize PN code acquisition in the Ku-band, whose forward-link PN clock is 3.03 Mchips/sec on a 1023-chip length sequence. Primary operational navigation will be provided by the Global Positioning System (GPS), which, after measuring transit time of the PN spread spectrum signal between a number of GPS satellites and itself, scales it by the velocity of light. GPS will enable position estimation accuracy to 30 feet and velocity estimation accuracy to 0.02 ft/sec.

Batson, B. H.↗
NASA NTRS2012

Optimal Dynamic Sub-Threshold Technique for Extreme Low Power Consumption for VLSI

For miniaturization of electronics systems, power consumption plays a key role in the realm of constraints. Considering the very large scale integration (VLSI) design aspect, as transistor feature size is decreased to 50 nm and below, there is sizable increase in the number of transistors as more functional building blocks are embedded in the same chip. However, the consequent increase in power consumption (dynamic and leakage) will serve as a key constraint to inhibit the advantages of transistor feature size reduction. Power consumption can be reduced by minimizing the voltage supply (for dynamic power consumption) and/or increasing threshold voltage (V(sub th), for reducing leakage power). When the feature size of the transistor is reduced, supply voltage (V(sub dd)) and threshold voltage (V(sub th)) are also reduced accordingly; then, the leakage current becomes a bigger factor of the total power consumption. To maintain low power consumption, operation of electronics at sub-threshold levels can be a potentially strong contender; however, there are two obstacles to be faced: more leakage current per transistor will cause more leakage power consumption, and slow response time when the transistor is operated in weak inversion region. To enable low power consumption and yet obtain high performance, the CMOS (complementary metal oxide semiconductor) transistor as a basic element is viewed and controlled as a four-terminal device: source, drain, gate, and body, as differentiated from the traditional approach with three terminals: i.e., source and body, drain, and gate. This technique features multiple voltage sources to supply the dynamic control, and uses dynamic control to enable low-threshold voltage when the channel (N or P) is active, for speed response enhancement and high threshold voltage, and when the transistor channel (N or P) is inactive, to reduce the leakage current for low-leakage power consumption.

Duong, Tuan A.↗
NASA NTRS1991

Single board system for fuzzy inference

The very large scale integration (VLSI) implementation of a fuzzy logic inference mechanism allows the use of rule-based control and decision making in demanding real-time applications. Researchers designed a full custom VLSI inference engine. The chip was fabricated using CMOS technology. The chip consists of 688,000 transistors of which 476,000 are used for RAM memory. The fuzzy logic inference engine board system incorporates the custom designed integrated circuit into a standard VMEbus environment. The Fuzzy Logic system uses Transistor-Transistor Logic (TTL) parts to provide the interface between the Fuzzy chip and a standard, double height VMEbus backplane, allowing the chip to perform application process control through the VMEbus host. High level C language functions hide details of the hardware system interface from the applications level programmer. The first version of the board was installed on a robot at Oak Ridge National Laboratory in January of 1990.

Symon, James R.↗