Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “chip scale”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 199 records · Page 11

Uncovering extreme nonlinear dynamics in solids through time-domain field analysis

Time-domain analysis of harmonic fields with sub-cycle resolution is now experimentally viable due to the emergence of sensitive, on-chip techniques for petahertz-scale optical-field sampling. We demonstrate how such a time-domain, field-resolved analysis uncovers the extreme nonlinear electron dynamics responsible for high-harmonic generation within solids. Time-dependent density functional theory was used to simulate harmonic generation from a solid-state band-gap system driven by near- to mid-infrared waveforms. Particular attention was paid to regimes where both intraband and interband emission mechanisms play a critical role in shaping the nonlinear response. We show that a time-domain analysis of the harmonic radiation fields identifies the interplay between intra- and interband dynamical processes underlying the nonlinear light generation. With further analysis, we show that changes to the dominant emission regime can occur after only slight changes to the peak driving intensity and central driving wavelength. Furthermore, time-domain analysis of harmonic fields also reveals, for the first time, the possibility of rapid changes in the dominant emission mechanism within the temporal window of the driving pulse envelope. Finally, we examine the experimental viability of performing time-domain analysis of harmonic fields with sub-cycle resolution using realistic parameters.

74 ATOMIC AND MOLECULAR PHYSICS↗

Two-Dimensional Systolic Array For Kalman-Filter Computing

Two-dimensional, systolic-array, parallel data processor performs Kalman filtering in real time. Algorithm rearranged to be Faddeev algorithm for generalized signal processing. Algorithm mapped onto very-large-scale integrated-circuit (VLSI) chip in two-dimensional, regular, simple, expandable array of concurrent processing cells. Processor does matrix/vector-based algebraic computations. Applications include adaptive control of robots, remote manipulators and flexible structures and processing radar signals to track targets.

Chang, Jaw John↗

Test aspects of the JPL Viterbi decoder

The generation of test vectors and design-for-test aspects of the Jet Propulsion Laboratory (JPL) Very Large Scale Integration (VLSI) Viterbi decoder chip is discussed. Each processor integrated circuit (IC) contains over 20,000 gates. To achieve a high degree of testability, a scan architecture is employed. The logic has been partitioned so that very few test vectors are required to test the entire chip. In addition, since several blocks of logic are replicated numerous times on this chip, test vectors need only be generated for each block, rather than for the entire circuit. These unique blocks of logic have been identified and test sets generated for them. The approach employed for testing was to use pseudo-exhaustive test vectors whenever feasible. That is, each cone of logid is tested exhaustively. Using this approach, no detailed logic design or fault model is required. All faults which modify the function of a block of combinational logic are detected, such as all irredundant single and multiple stuck-at faults.

Breuer, M. A.↗

Distributed Quantum Error Correction for Chip-Level Catastrophic Errors

Quantum error correction holds the key to scaling up quantum computers. Cosmic ray events severely impact the operation of a quantum computer by causing chip-level catastrophic errors, essentially erasing the information encoded in a chip. Here, in this work, we present a distributed error correction scheme to combat the devastating effect of such events by introducing an additional layer of quantum erasure error correcting code across separate chips. We show that our scheme is fault tolerant against chip-level catastrophic errors and discuss its experimental implementation using superconducting qubits with microwave links. Our analysis shows that in state-of-the-art experiments, it is possible to suppress the rate of these errors from 1 per 10 s to less than 1 per month.

97 MATHEMATICS AND COMPUTING↗

Low-latency NuMI Trigger for the CHIPS-5 Neutrino Detector

The CHIPS R&D project aims to develop affordable water Cherenkov detectors for large-scale underwater installations. In 2019, a 5kt prototype detector CHIPS-5 was deployed in northern Minnesota to study neutrinos generated by the nearby NuMI beam. This contribution presents a dedicated low-latency time distribution system for CHIPS-5 that delivers timing signals from the Fermilab accelerator to the detector with sub-nanosecond precision. Exploiting existing NOvA infrastructure, the time distribution system achieves this only with open-source software and conventional network elements. In a time-of-flight study, the presented system has reliably offered a time budget of $610 \pm 330\text{ ms}$ for on-site triggering. This permits advanced analysis in real-time as well as a novel hardware-assisted active triggering mode, which reduces DAQ computing load and network bandwidth outside triggered time windows.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗

A laser plotting system for VLSI chip layouts

One of the most time consuming facets of custom Very Large Scale Integration (VLSI) design is obtaining hardcopy plots of the mask geometries of cells and chips. The traditional method of generating these plots is to use a multicolor pen plotter. Pen plotters are inherently slow and the plotting speed increases linearly with the number of edges that must be plotted. A moderate custom chip design at the Jet Propulsion Laboratory (JPL) now consists of more than 200,000 such edges and can take as much as eight hours to plot using a pen plotter. Software is described that was written at JPL to produce similar plots using a laser printer. It is shown that, for rather small layouts, the laser printer can provide nearly instantaneous turnaround. For moderate to large chip designs, the laser printer provides a factor of five or more improvement is speed over pen plotting.

Deutsch, L. J.↗

Superconducting qubits in a flip-chip architecture

Flip-chip architectures have recently enabled significant scaling-up of multi-qubit circuits and have been used to assemble hybrid quantum systems that combine different substrates, for example, for quantum acoustics experiments. The standard flip-chip method uses superconducting galvanic connections between two substrates, typically implemented using sophisticated indium wafer-bonding systems, which give highly reliable and temperature-cyclable assemblies, but are expensive, somewhat inflexible in design, and require robust substrates that can sustain the large compressive forces required to cold-weld the indium bonds. A much simpler method is to assemble dies using very low-force contacts and air-dried adhesives, although this does not provide a galvanic contact between the dies. In this work, we demonstrate that the latter technique can be used to reliably couple superconducting qubit circuits, in which the qubits are on separate dies, without the need for a galvanic connection. We demonstrate full vector qubit control of each qubit on each of the two dies, with high-fidelity single-shot readout, and further demonstrate entanglement-generating excitation swaps as well as benchmark a controlled-Z entangling gate between the two qubits on the two dies. This exemplifies a simple and inexpensive assembly method for two-plus-one-dimensional quantum circuit integration that supports the use of delicate or unusually shaped substrates.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Large ejecta fragments from asteroids

The asteroid 4 Vesta, with its unique basaltic crust, remains a key mystery of planetary evolution. A localized olivine feature suggests excavation of subcrustal material in a crater or impact basin comparable in size to the planetary radius (R(sub vesta) is approximately = 280 km). Furthermore, a 'clan' of small asteroids associated with Vesta (by spectral and orbital similarities) may be ejecta from this impact 151 and direct parents of the basaltic achondrites. To escape, these smaller (about 4-7 km) asteroids had to be ejected at speeds greater than the escape velocity, v(sub esc) is approximately = 350 m/s. This evidence that large fragments were ejected at high speed from Vesta has not been reconciled with the present understanding of impact physics. Analytical spallation models predict that an impactor capable of ejecting these 'chips off Vesta' would be almost the size of Vesta! Such an impact would lead to the catastrophic disruption of both bodies. A simpler analysis is outlined, based on comparison with cratering on Mars, and it is shown that Vesta could survive an impact capable of ejecting kilometer-scale fragments at sufficient speed. To what extent does Vesta survive the formation of such a large crater? This is best addressed using a hydrocode such as SALE 2D with centroidal gravity to predict velocities subsequent to impact. The fragmentation outcome and velocity subsequent to the impact described to demonstrate that Vesta survives without large-scale disassembly or overturning of the crust. Vesta and its clan represent a valuable dataset for testing fragmentation hydrocodes such as SALE 2D and SPH 3D at planetary scales. Resolution required to directly model spallation 'chips' on a body 100 times as large is now marginally possible on modern workstations. These boundaries are important in near-surface ejection processes and in large-scale disruption leading to asteroid families and stripped cores.

Asphaug, E.↗

A new VLSI architecture for a single-chip-type Reed-Solomon decoder

A new very large scale integration (VLSI) architecture for implementing Reed-Solomon (RS) decoders that can correct both errors and erasures is described. This new architecture implements a Reed-Solomon decoder by using replication of a single VLSI chip. It is anticipated that this single chip type RS decoder approach will save substantial development and production costs. It is estimated that reduction in cost by a factor of four is possible with this new architecture. Furthermore, this Reed-Solomon decoder is programmable between 8 bit and 10 bit symbol sizes. Therefore, both an 8 bit Consultative Committee for Space Data Systems (CCSDS) RS decoder and a 10 bit decoder are obtained at the same time, and when concatenated with a (15,1/6) Viterbi decoder, provide an additional 2.1-dB coding gain.

Hsu, I. S.↗

VLSI-Chip Tester

Compact test set integrated in computer-aided design system. Test set performs functional tests on very-large-scale integrated (VLSI) circuits. Makes tests from points within VLSI chip as well as at input and output pins. Used for quality control and design; in latter capacity, checks internal logic functions on chip and feed results directly to computer-aided design system for correction. Also simulates operation of chip design before chip is made. VLSI Tester contains three power supplies, control logic, and standard multibus circuit board in aluminum chassis. Chassis fits under platform of microprobe station. Multibus board links tester to interactive terminals and to host computer.

Deutsch, Leslie J.↗

An on-chip phased array for non-classical light

Abstract Quantum science and technology can offer fundamental enhancements in sensing, communications and computing. The expansion from wired to wireless links is an exciting prospect for quantum technologies. For classical technologies, the advent of phased arrays enabled directional and adaptive wireless links by manipulating electromagnetic waves over free space. Here we demonstrate a phased array system on a chip that can receive, image and manipulate non-classical light over free space. We use an integrated photonic-electronic system with more than 1000 functional components on-chip to detect squeezed light. By integrating an array of 32 sub-wavelength engineered metamaterial antennas, we demonstrate a direct free-space-to-chip interface for reconfigurable quantum links. On the same chip, we implement a large-scale array of quantum-limited coherent receivers that can resolve non-classical signals simultaneously across 32 channels. With coherent readout and manipulation of these signals, we demonstrate 32-pixel imaging and spatially configurable reception of squeezed light over free space. Our work advances wireless quantum technologies that could enable practical applications in quantum communications and sensing.

Science & Technology - Other Topics↗

Silicon Nanosheets as Candidates for Silicon-Based Optoelectronics

The growth in computational ability over the past decades has positively impacted global development, the economy, healthcare, and science. As on-chip components are approaching the atomic scale, alternative paradigms are needed to address the thermal and electronic issues that impose bottlenecks for computing. One approach to address this is with optoelectronics. However, silicon—the backbone of microelectronics—is a poor choice due to its indirect bandgap, while existing optoelectronic materials are incompatible with CMOS infrastructure. Monolayer silicon nanosheets (SiNSs) are an intriguing material that exhibit photoluminescence, and are compositionally-compatible with the CMOS process. Here, we synthesize and characterize monolayer SiNSs, and show spectroscopic evidence that they exhibit a quasi-direct bandgap, which is corroborated by DFT calculations. We probe their thermal stability, demonstrating their structure and photoluminescence are stable beyond the required operating temperatures for computing applications. These optoelectronic properties, CMOS-compatibility, and stability make SiNSs a viable candidate for silicon-based photonics.

Ryan, Bradley↗

Development of a Novel Magnesium Alloy for Thixomolding® of Automotive Components (Final Report)

Magnesium (Mg) alloy die-castings are increasingly used in the automobile industry to achieve cost effective mass reduction, especially in systems where multiple components can be integrated into a single thin wall die-casting. However, there are several component quality restrictions in thin-walled Mg die castings, including variability in dimensional accuracy, part-to-part variation in mechanical properties, and porosity in the final part, which has limited the continued growth of die-cast components in the automobile industry. An alternative to die-casting is the process of thixomolding®. While the die-casting process relies on filling a mold at high speeds with the alloy in the completely molten state, the thixomolding® process fills a mold with a thixotropic alloy in a semi-solid slurry state at a temperature between the liquidus and solidus temperatures. Ideally, the material should be ~30–65% solid rather than being completely liquid at the beginning of the injection process. Advantages of the thixomolding® process include a finer grain structure, lower porosity, improved dimensional accuracy, improved part-to part consistency, improved mechanical properties, particularly ductility in the component, the ability to reduce wall thickness for mass savings, and longer tool life due to lower process temperatures. The objective of this collaborative project between Oak Ridge National Laboratory, FCA US LLC, and Leggera Technologies was to develop one or more novel Mg alloys more suitable for thixomolding® automotive structural components than the current die-casting alloys used for this process. The primary interest was to improve ductility while maintaining tensile and fatigue strengths, as these are properties that are critical for use in body and chassis structural applications. Since good corrosion resistance is also desirable for this application, this property was also considered when evaluating promising alloy compositions. An initial evaluation of existing components thixomolded® using AM60 was performed and microstructure, and tensile properties were evaluated for the baseline alloy. Targets were established for ease of processing (characterized by the melting range defined as the difference between the liquidus and the solidus), strength, and ductility. Computational modeling was used to identify promising alloys and selected alloys were cast in laboratory scale heats. Properties measured from laboratory scale heats were used to down-select two alloys for further evaluation and component fabrication. Two alloys were prepared in industrial scale heats, cut into small pieces (chips), and thixomolding® trials were initiated. Trial components were successfully fabricated using one alloy composition, but it was concluded that further refinement of the thixomolding® process parameters are required to successfully fabricate component using second alloy. Microstructure and mechanical properties were evaluated on the material removed from the fabricated component and properties were compared to the baseline alloy. Although mechanical properties of the alloys showed improvement over the baseline alloy, it was determined that modifications to the thixomolding® process would result in better microstructure control with further improvement in properties leading to successful commercialization. A provisional patent application has already been filed on the new alloys developed as part of the project.

36 MATERIALS SCIENCE↗

Testing interconnected VLSI circuits in the Big Viterbi Decoder

The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

Onyszchuk, I. M.↗

Quantum criticality using a superconducting quantum processor

Quantum criticality emerges from the collective behavior of many interacting quantum particles, often at the transition between different phases of matter. It is one of the cornerstones of condensed matter physics, which we access on noisy intermediate-scale (NISQ) quantum devices by leveraging a dynamically driven phenomenon. Here we probe the critical properties of the one-dimensional quantum Ising model on a programmable superconducting quantum chip via a Kibble-Zurek process, obtain scaling laws, and estimate critical exponents despite inherent sources of errors on the hardware. In addition, we investigate how the improvement of NISQ computers (more qubits, less noise) will consolidate the computation of those universal physical properties. A one-parameter noise model captures the effect of imperfections and reproduces the experimental data. Its systematic study reveals that the noise, analogously to temperature, induces a new length scale in the system. We introduce and successfully verify modified scaling laws, directly accounting for the noise without any prior knowledge. It makes data analyses for extracting physical properties transparent to noise. By understanding how imperfect quantum hardware modifies the genuine properties of quantum states of matter, we enhance the power of NISQ processors considerably for addressing quantum criticality and potentially other phenomena and algorithms.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

Chip level modeling of LSI devices

The advent of Very Large Scale Integration (VLSI) technology has rendered the gate level model impractical for many simulation activities critical to the design automation process. As an alternative, an approach to the modeling of VLSI devices at the chip level is described, including the specification of modeling language constructs important to the modeling process. A model structure is presented in which models of the LSI devices are constructed as single entities. The modeling structure is two layered. The functional layer in this structure is used to model the input/output response of the LSI chip. A second layer, the fault mapping layer, is added, if fault simulations are required, in order to map the effects of hardware faults onto the functional layer. Modeling examples for each layer are presented. Fault modeling at the chip level is described. Approaches to realistic functional fault selection and defining fault coverage for functional faults are given. Application of the modeling techniques to single chip and bit slice microprocessors is discussed.

Armstrong, J. R.↗

A VLSI single chip 8-bit finite field multiplier

A Very Large Scale Integration (VLSI) architecture and layout for an 8-bit finite field multiplier is described. The algorithm used in this design was developed by Massey and Omura. A normal basis representation of finite field elements is used to reduce the multiplication complexity. It is shown that a drastic improvement was achieved in this design. This multiplier will be used intensively in the implementation of an 8-bit Reed-Solomon decoder and in many other related projects.

Deutsch, L. J.↗