Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “bit error rate”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 199 records · Page 11
All sourcesNASA NTRSDOE OSTI
NASA NTRS1979

Pre-A/D filter and AGC requirements for multimegabit telemetry data detection

A candidate pre-Analog to Digital filter bandwidth versus data rate design is presented for the multimegabit telemetry demodulator/detector. The design is based on considerations of Analog to Digital bias, quantization errors, and automatic gain control effects, as well as the deleterious effects of filtering. Two methods of gain control of the input level to the analog to Digital converter are considered. The first method uses a particular value of gain, according to which bandwidth is selected. The second method uses a second narrowband noncoherent Automatic Gain Controls (in the LPF bandwidth) to attempt to keep the Analog to Digital input level constant. This second method reduces the bit error rate degradation slightly but appears to be more difficult to implement.

Holmes, J. K.↗
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing, a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study, which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating, and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In this research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1996

High-Speed Soft-Decision Decoding of Two Reed-Muller Codes

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RNI subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second (Mbps). The combination of a large number of states and a hi ch data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high-speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these sub-trellises.

Lin, Shu↗
NASA NTRS1996

Circuit Design Approaches for Implementation of a Subtrellis IC for a Reed-Muller Subcode

In his research, we have proposed the (64, 40, 8) subcode of the third-order Reed-Muller (RM) code to NASA for high-speed satellite communications. This RM subcode can be used either alone or as an inner code of a concatenated coding system with the NASA standard (255, 233, 33) Reed-Solomon (RS) code as the outer code to achieve high performance (or low bit-error rate) with reduced decoding complexity. It can also be used as a component code in a multilevel bandwidth efficient coded modulation system to achieve reliable bandwidth efficient data transmission. This report will summarize the key progress we have made toward achieving our eventual goal of implementing a decoder system based upon this code. In the first phase of study, we investigated the complexities of various sectionalized trellis diagrams for the proposed (64, 40, 8) RM subcode. We found a specific 8-trellis diagram for this code which requires the least decoding complexity with a high possibility of achieving a decoding speed of 600 M bits per second(Mbps). The combination of a large number of states and a high data rate will be made possible due to the utilization of a high degree of parallelism throughout the architecture. This trellis diagram will be presented and briefly described. In the second phase of study which was carried out through the past year, we investigated circuit architectures to determine the feasibility of VLSI implementation of a high- speed Viterbi decoder based on this 8-section trellis diagram. We began to examine specific design and implementation approaches to implement a fully custom integrated circuit (IC) which will be a key building block for a decoder system implementation. The key results will be presented in this report. This report will be divided into three primary sections. First, we will briefly describe the system block diagram in which the proposed decoder is assumed to be operating and present some of the key architectural approaches being used to implement the system at high speed. Second, we will describe details of the 8-trellis diagram we found to best meet the trade-offs between chip and overall system complexity. The chosen approach implements the trellis for the (64, 40, 8) RM subcode with 32 independent sub-trellises. And third, we will describe results of our feasibility study on the implementation of such an IC chip in CMOS technology to implement one of these subtrellises.

Lin, Shu↗
NASA NTRS1984

On the passage of high-level pulsed radio frequency interference through a nonlinear satellite transponder

Attention is given to the uncoded bit error rate (BER) performance of a satellite communications system whose modulation scheme is binary PSK and whose transponder contains an arbitrary amplitude nonlinearity, all in the presence of high level pulsed radio frequency interference (RFI). A general approach is presented for direct BER evaluations, in contrast to other approaches which may employ SNR suppression factors. The computed results are based on arbitrarily specified RFI scenarios, in the presence of hard limiter, clipper, or blanker amplitude nonlinearities. Performance curves demonstrate the superiority of an appropriately chosen blanker when the RFI environment is most severe. The results obtained also pertain to the sensitivity of performance to the information bit rate, signal power variations, and the ratio of CW to noise content. The CW effects are found to be the most severe.

Weinberg, A.↗
NASA NTRS1971

Performance results for a hybrid coding system.

Results of computer simulation studies of the hybrid pull-up bootstrap decoding algorithm, using a constraint length 24, nonsystematic, rate 1/2 convolutional code for the symmetric channel with both binary and eight-level quantized outputs. Computational performance was used to measure the effect of several decoder parameters and determine practical operating constraints. Results reveal that the track length may be reduced to 500 information bits with small degradation in performance. The optimum number of tracks per block was found to be in the range from 7 to 11. An effective technique was devised to efficiently allocate computational effort and identify reliably decoded data sections. Long simulations indicate that a practical bootstrap decoding configuration has a computational performance about 1.0 dB better than sequential decoding and an output bit error rate about .0000025 near the R sub comp point.

Hoffman, L. B.↗
NASA NTRS1992

Rate 3/4 coded 16-QAM for uplink applications

First phase development of an advanced modulation technology which synergistically combines coding and modulation to achieve 2 bits per second per Hertz bandwidth efficiency in satellite demodulators is nearing completion. A proof-of-concept model is being developed to demonstrate technology feasibility, establish practical bandwidth efficiency limitations, and provide a data base for the design and development of engineering model satellite demodulators. The basic considerations leading to the choice of 4 x 4 quadrature amplitude modulation (16-QAM) and its associated coding format are discussed, along with the basic implementation of the carrier and clock recovery, automatic gain control, and decoding process. Preliminary performance results are presented. Spectra for the modulated signal shows the effects of the square root Nyquist filters in the modulation. Bit error rate (BER) results for the encoder/decoder subsystem show near ideal results, although power consumption is high and baseband BER performance of the Nyquist filter set is poor. Recommendations regarding the present system to improve BER performance and acquisition speed are given.

Mrozek, Eric M.↗
NASA NTRS1992

Rate 8/9 coded 8-PSK system for downlink applications

An advanced Coded Trellis Modulation (CTM) System which achieves a 2 bits/s/Hz bandwidth efficiency at an information rate of 200 Mbit/s while minimizing satellite power requirements, was developed for downlink earth station applications. The CTM system employs a high-speed rate 8/9 convolutional code with Viterbi decoding and an 8-Phase Shift Keying (PSK) modem. The minimum Euclidean distance between the modulated waveforms corresponding to the information sequences are maximized in order to maximize the noise immunity of the system. Nyquist filters with a square-root of 40 percent roll-off are used at the transmit and receive sides of the modem in order to minimize intersymbol interference, adjacent channel interference, and distortion at the nonlinear satellite power amplifier. The use of a coded system here also minimizes the effects of co-channel interference. The developed performance of the hardware system was measured to achieve within 1.5 dB from theory at a bit error rate of 5 x 10(exp -7) over an additive white Gaussian noise channel.

Fang, Russell↗
NASA NTRS1993

SATCOM simulator speeds MSS deployment and lowers costs

Mobile satellite systems (MSS) are being proposed and licensed at an accelerating rate. How can the design, manufacture, and performance of these systems be optimized at costs that allow a reasonable return on investment? The answer is the use of system simulation techniques beginning early in the system design and continuing through integration, pre- and post-launch monitoring, and in-orbit monitoring. This paper focuses on using commercially available, validated simulation instruments to deliver accurate, repeatable, and cost effective measurements throughout the life of a typical mobile satellite system. A satellite communications test set is discussed that provides complete parametric test capability with a significant improvement in measurement speed for manufacturing, integration, and pre-launch and in-orbit testing. The test set can simulate actual up and down link traffic conditions to evaluate the effects of system impairments, propagation and multipath on bit error rate (BER), channel capacity and transponder and system load balancing. Using a standard set of commercial instruments to deliver accurate, verifiable measurements anywhere in the world speeds deployment, generates measurement confidence, and lowers total system cost.

Carey, Tim↗
NASA NTRS2002

On-Orbit Performance Verification and End-to-End Characterization of the TDRS-H Ka-Band Communications Payload

In June 2000, NASA launched the first of three next generation Tracking and Data Relay Satellites (TDRS-H) equipped with a Ka-band forward and return service capability. This Ka-band service supports forward data rates up to 25 Mb/sec using the 22.55 - 23.55 GHz space-to-space allocation. Return services are supported via channel bandwidths of 225 and 650 MHz for data rates up to 800 Mb/sec (QPSK) using the 25.25 - 27.5 GHz space-to-space allocation. As part of NASA's acceptance of the TDRS-H spacecraft, an extensive on-orbit calibration, verification and characterization effort was performed to ensure that on-orbit spacecraft performance is within specified limits. This process verified the compliance of the Ka-band communications payload with all performance specifications and demonstrated an end-to-end Ka-band service capability. This paper summarizes the results of the TDRS-H Ka-band communications payload on-orbit performance verification and end-to-end service characterization. Performance parameters addressed include Effective Isotropically Radiated Power (EIRP), antenna Gain-to-System Noise Temperature (G/T), antenna gain pattern, frequency tunability and accuracy, channel magnitude response, and Ka-band service Bit-Error-Rate (BER) performance.

Toral, Marco↗
NASA NTRS2002

On-Orbit Performance Verification and End-To-End Characterization of the TDRS-H Ka-band Communications Payload

In June 2000, NASA launched the first of three next generation Tracking and Data Relay Satellites (TDRS-H) equipped with a Ka-band forward and return service capability. This Ka-band service supports forward data rates of up to 25 Mb/sec using the 22.55-23.55 GHz space-to-space allocation. Return services are supported via channel bandwidths of 225 and 650 MHz for data rates up to at least 800 Mb/sec using the 25.25 - 27.5 GHz space-to-space allocation. As part of NASA's acceptance of the TDRS-H spacecraft, an extensive on-orbit calibration, verification and characterization effort was performed to ensure that on-orbit spacecraft performance is within specified limits. This process verified the compliance of the Ka-band communications payload with all performance specifications, and demonstrated an end-to-end Ka-band service capability. This paper summarizes the results of the TDRS-H Ka-band communications payload on-orbit performance verification and end-to-end service characterization. Performance parameters addressed include antenna gain pattern, antenna Gain-to-System Noise Temperature (G/T), Effective Isotropically Radiated Power (EIRP), antenna pointing accuracy, frequency tunability, channel magnitude response, and Ka-band service Bit-Error-Rate (BER) performance.

Toral, Marco↗
NASA NTRS2020

Q4 – A CubeSat Mission to Demonstrate Omnidirectional Optical Communications

We are proposing a technology demonstration mission for JPL’s Inter-Satellite Optical Communicator (ISOC). The ISOC has the potential to enable up to 1 Gbps data rates over a distance up to 200 km in free space. Key features of the ISOC include full sky coverage and the ability to maintain multiple links simultaneously. The Q4 mission consists of (4) 6U CubeSats furnished with ISOCs to demonstrate high data rate communications among the spacecraft. More specifically, we seek to demonstrate the omnidirectionality of the ISOC by providing simultaneous optical links between one spacecraft and the other three. Q4 will be a demonstrator for small spacecraft swarm capabilities. Following a proposed deployment from the ISS, the CubeSats will utilize their onboard thrusters to enter their desired orbit. The orbit consists of one “leader” spacecraft in a circular orbit with a 400 km LEO altitude and three “follower” spacecraft in slightly elliptical orbits rotating azimuthally about the leader. The main mission will consist of three consecutive phases: First, the spacecraft will demonstrate pointing, acquisition, and tracking using newly developed protocols. Next, link establishment and different channel access methods (CDMA and TDMA) will be tested. Finally, Delay Tolerant Network protocols will be implemented to allow fast data sharing among the spacecraft. The distance between the communicating spacecraft will be increased as the mission progresses to characterize the link quality as a function of distance. All communications over the course of the mission will be recorded and analyzed on the ground using bit error rate as a metric for success. The current design for each the four Q4 CubeSats contains an XACT advanced ADCS system for precision beam pointing. Other components currently under consideration include MiPS cold gas thrusters for orbital maneuvering and gimbaled eHaWK 84W solar arrays. In this paper we present design considerations for the Q4 CubeSats, link budget calculations, results from preliminary mission analysis, and expected results.

Velazco, Jose E↗
NASA NTRS1994

Advanced technology for a satellite multichannel demultiplexer/demodulator

Satellite on-board processing is needed to efficiently service multiple users while at the same time minimizing earth station complexity. The processing satellite receives a wideband uplink at 30 GHz and down-converts it to a suitable intermediate frequency. A multichannel demultiplexer then separates the composite signal into discrete channels. Each channel is then demodulated by bulk demodulators, with the baseband signals routed to the downlink processor for retransmission to the receiving earth stations. This type of processing circumvents many of the difficulties associated with traditional bent-pipe repeater satellites. Uplink signal distortion and interference are not retransmitted on the downlink. Downlink power can be allocated in accordance with user needs, independent of uplink transmissions. This allows the uplink users to employ different data rates as well as different modulation and coding schemes. In addition, all downlink users have a common frequency standard and symbol clock on the satellite, which is useful for network synchronization in time division multiple access schemes. The purpose of this program is to demonstrate the concept of an optically implemented multichannel demultiplexer (MCD). A proof-of-concept (POC) model has been developed which has the ability to receive a 40 MHz wide composite signal consisting of up to 1000 40 kHz QPSK modulated channels and perform the demultiplexing process. In addition a set of special test equipment (STE) has been configured to evaluate the performance of the POC model. The optical MCD is realized as an acousto-optic spectrum analyzer utilizing the capability of Bragg cells to perform the required channelization. These Bragg cells receive an optical input from a laser source and an RF input (the signal). The Bragg interaction causes optical output diffractions at angles proportional to the RF input frequency. These discrete diffractions are optically detected and output to individual demodulators for baseband conversion. Optimization of the MCD design was conducted in order to achieve a compromise between two opposing sources of signal degradation: adjacent channel interference and intersymbol interference. The system was also optimized to allow simple, inexpensive ground stations communications with the MCD. These design goals led to the realization of a POC MCD which demonstrates the demultiplexing function with minimal signal degradation. Performance evaluation results using the STE equipment indicate that the dynamic range of the demultiplexer in the presence of adjacent and multiple channel loading is 40 - 50 dB. Measured bit error rate (BER) probabilities varied from the predicted theoretical results by one dB or less. The performance of the proof-of-concept model indicate that the development of a space qualified optically implemented MCD are feasible. The advantages to such an implementation include reduced size, weight and power and increased reliability when compared with electronic approaches. All of these factors are critical to on-board satellite processors. Further optimization can be conducted which trade ground station complexity and MCD performance to achieve desired system results.

Abramovitz, Irwin J.↗
DOE OSTI2023

A superconducting nanowire binary shift register

We present a design for a superconducting nanowire binary shift register, which stores digital states in the form of circulating supercurrents in high-kinetic-inductance loops. Adjacent superconducting loops are connected with nanocryotrons, three-terminal electrothermal switches, and fed with an alternating two-phase clock to synchronously transfer the digital state between the loops. A two-loop serial-input shift register was fabricated with thin-film NbN and a bit error rate of less than 10 –4 was achieved, when operated at a maximum clock frequency of 83 MHz and in an out-of-plane magnetic field of up to 6 mT. A shift register based on this technology offers an integrated solution for low-power readout of superconducting nanowire single photon detector arrays and is capable of interfacing directly with room-temperature electronics and operating unshielded in high magnetic field environments.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2023

A nanocryotron memory and logic family

The development of superconducting electronics based on nanocryotrons has been limited so far to few device circuits, in part due to the lack of standard and robust logic cells. Here, we introduce and experimentally demonstrate designs for a set of nanocryotron-based building blocks that can be configured and combined to implement memory and logic functions. The devices were fabricated by patterning a single superconducting layer of niobium nitride and measured in liquid helium on a wide range of operating points. The tests show 10 - 4 bit error rates with above ± 20 % margins up to 50 MHz and the possibility of operating under the effect of an out-of-plane 36 mT magnetic field, with ± 30 % margins at 10 MHz. Additionally, we designed and measured an equivalent delay-flip-flop made of two memory cells to show the possibility of combining multiple building blocks to make larger circuits. These blocks may constitute a solid foundation for the development of nanocryotron logic circuits and finite-state machines with potential applications in the integrated processing and control of superconducting nanowire single-photon detectors.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2020

Influence of birefringent fibre joints on the visibility drift in a Mach – Zehnder interferometer

It is shown that imperfect joints of linear birefringent fibres in a fibre interferometer may result in an uncontrolled visibility drift under varying environmental conditions even with a standard phase matching device. As an example, a double Mach – Zehnder interferometer is considered, which is employed in schemes of quantum key distribution. Results of numerical simulation demonstrate the standard deviation of the quantum bit error rate (QBER), which is comparable to an average QBER value. (paper)

36 MATERIALS SCIENCE↗
DOE OSTI2022

The Octopus processor for the CMS L1 muon trigger for High Luminosity LHC

The upgraded L1 muon trigger system of the CMS experiment in the High Luminosity Large Hadron Collider is based on custom processors featuring large Field Programmable Gate Arrays (FPGAs) connected by large numbers of optical links. These provide the I/O bandwidth and power necessary to process the complex algorithms used during the collection of physics data. The design and performance requirements of these processors creates significant challenges in signal integrity, power delivery, and thermal management. In this paper we describe the Octopus processor, featuring a large Xilinx Virtex Ultrascale+ FPGA and up to 128 links interfaced to optics through high quality twin-ax copper cables. Results on signal integrity at 25 Gb/s and the first demonstration of 50+ Gb/s links with pluggable optics in CMS are also shown, demonstrating bit error rates below 10 –15 at a 95% confidence level. The thermal performance is measured inside an Advanced-TCA crate with acceptable thermal margins up to 200 W of chip power. Future improvements are mentioned, potentially allowing operation at up to 300 W.

Instruments & Instrumentation↗