Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “MOSFETs”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

192 records · Page 11
All sourcesNASA NTRSDOE OSTI
DOE OSTI2020

Packaging Development for a 1200V SiC BiDFET Switch Using Highly Thermally Conductive Organic Epoxy Laminate

A novel 1.2 kV/10A, 4H-SiC monolithic, bidirectional switch has been developed for use in cycloconverter applications to facilitate high-frequency direct AC-to-AC power conversion and enables new power converter topologies. A new packaging solution, utilizing a 100 µm flexible polyimide organic laminate substrate is developed to mitigate thermo-mechanical stress during power cycling and enable smaller form factor and lower cost. Multiphysics simulations and static tests were conducted to show performance characterization of the module and compare it against metallic substrates. A new organic laminate epoxy resin composite dielectric (ERCD) is also evaluated for superior thermal performance and shows 63% reduction in junction to case resistance compared to DBC substrates.

Silicon Carbide, Bi-directional switch, BiDFET, MO↗
DOE OSTI2020

Methodology of Low Inductance Busbar Design for Three-Level Converters

Three-level (3L) converters are more susceptible to parasitics compared with two-level converters because of their complicated structure with multiple switching loops. In this article, the methodology of busbar layout design for 3L converters based on the magnetic cancellation effect is presented. The methodology can fit for 3L converters with symmetric and asymmetric configurations. A detailed design example is provided for a high-power 3L-active neutral point clamped (ANPC) converter, which includes the module selection, busbar layout, and dc-link capacitor placement. The loop inductance of the busbar is verified with simulation, impedance measurements, and converter experiments. Furthermore, the results match with each other, and the inductances of short and long loops are 6.5 and 17.5 nH, respectively, which are significantly lower than the busbars of NPC-type converters in other references.

42 ENGINEERING↗
DOE OSTI2023

Single-Phase Jet Impingement Cooling for a Power-Dense Silicon Carbide Power Module

The adoption of silicon carbide (SiC) devices in the electric vehicle (EV) industry is increasing due to their superior performance over silicon devices. SiC devices enable further miniaturization of EV inverters, increasing their power density, which results in thermal management challenges. Here in this paper, the limits of single-phase jet impingement cooling are explored for an automotive SiC power module. We propose embedding pin fins in the direct-bonded-copper (DBC) substrate of the power module package using laser powder bed fusion additive manufacturing. The thermalhydraulic performance of the DBC-embedded pin fins is compared against folded fins that are directly soldered to the DBC substrate. A heat conduction analysis was conducted on a SiC package to determine the target heat transfer coefficient (HTC) for the heat sink. A water-ethylene glycol (WEG) jet impingement on the proposed concepts was studied using unit-cell models to achieve the target HTC. The studied designs put emphasis on the reliability and manufacturability requirements of the automotive industry. The thermal performance of DBC-embedded pin fins outperformed the DBC-soldered folded fins. The performance of the DBC-embedded pin fins is benchmarked against WEG-based cooling systems of commercial EVs. With the proposed cooling solution, we have shown a pathway of reducing the specific thermal resistance by 75% compared to BMW i3 thermal management system without any penalty on pressure drop or parasitic power.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2020

DFF Layout Variations in CMOS SOI—Analysis of Hardening by Design Options

Four D flip-flop (DFF) layouts were created from the same schematic in Sandia National Laboratories’ CMOS7 silicon-on-insulator (SOI) process. Single-event upset (SEU) modeling and testing showed an improved response with the use of shallow (not fully bottomed) N-type metal-oxide-semiconductor field-effect transistors (NMOSFETs), extending the size of the drain implant and increasing the critical charge of the transmission gates in the circuit design and layout. This research also shows the importance of correctly modeling nodal capacitance, which is a major factor determining SEU critical charge. Accurate SEU models enable the understanding of the SEU vulnerabilities and how to make the design more robust.

42 ENGINEERING↗
DOE OSTI2021

The Impact of Inverter Dead-Time in Single-Phase Wireless Power Transfer Systems

In this paper, the effect of the dead-time on a single-phase wireless power transfer system is studied in detail. In practice, the dead-time is always placed between the complementary switching pulses of the inverter phase-leg. At higher operating frequencies, the dead-time issues in the resonant inverter become critical, especially as the power level increases. The detailed analysis of the dead-time on a wireless power transfer system is discussed for different operating conditions of the inverter duty-cycle and power factor. The switching characteristics of the wireless power transfer system inverter are analyzed, and the notch phenomenon that appears at the output of the inverter is also discussed. A notch equation based on the observations is derived to predict the notch occurrence during the system operation. Furthermore, the mathematical expressions are presented for different notch conditions. Subsequently, the effect of the notches on the sensitivity and the power transfer of the series-series compensated wireless power transfer system is analyzed. Finally, the approach is verified experimentally on an 8 kW wireless power transfer system prototype, and the results are compared with the theoretical analysis.

42 ENGINEERING↗
DOE OSTI2025

Organic Direct-Bonded-Copper-Based Rapid Prototyping for Silicon Carbide Power Module Packaging

Silicon carbide (SiC) power devices are playing ever- growing roles in high-power-density power electronics converters by offering benefits such as high voltage rating, fast transients, and high thermal performance. Organic direct-bonded copper (ODBC)-based packaging, due to its ductility and ease of han- dling, allows the possibility of a more flexible layout design that may better tap the potential of SiC benefits. In this work, an ODBC-based prototyping routine is developed that accelerates the iterations of packaging layout design with low cost. The properties of ODBC and its handling are briefly introduced, and tools and fabrication steps are explained. Following this routine, a 1.2-kV SiC half-bridge power module is designed and fabricated with the focus on sub-nanohenry ultra-low loop inductance. Simulation and experimental validation are also conducted.

25 ENERGY STORAGE↗
DOE OSTI2025

Thermal Management for Planar Package Power Electronics (CRADA Final Report)

The National Renewable Energy Laboratory (NREL) and John Deere Electronic Solutions (JDES) collaborated to develop and evaluate computer models and simulations related to the thermal performance of semiconductor device packaging for an inverter of an off-road vehicle ("Semiconductor Packaging"). The objective of the research was for NREL and JDES to develop a two or three-dimensional computer-aided design model of the Semiconductor Packaging ("Computer Model") for thermal performance evaluation in a simulation. The project developed computer models of a Semiconductor Package of silicon-carbide semiconductor devices with appropriate thermal dissipation via one or more of the following thermal features: a double-sided planar cooling configuration, an air-cooled configuration, a liquid-cooled configuration for off-road inverter applications in a relevant simulated operating environment. It is noted that surface area and prototype product embodiment consisting of air-cooled and liquid-cooled configurations may and may not be in direct contact with power semiconductor chips. The idea was to explore and develop packaging and thermal management technology for power semiconductors that was most effective in the performance yet had least burden in overall product cost for a given application.

33 ADVANCED PROPULSION SYSTEMS↗
DOE OSTI2021

Model Reduction by Generalized Falk Method for Efficient Field-Circuit Simulations

The Generalized Falk Method (GFM) for coordinate transformation, together with two model-reduction strategies based on this method, are presented for efficient coupled field-circuit simulations. Each model-reduction strategy is based on a decision to retain specific linearly-independent vectors, called trial vectors, to construct a vector basis for coordinate transformation. The reduced-order models are guaranteed to be stable and passive since the GFM is a congruence transformation of originally symmetric positive definite systems. We also show that, unlike the Pad´e-via-Lanczos (PVL) method, the GFM does not generate unstable positive poles while reducing the order of circuit problems. Further, the proposed GFM is also faster when compared to methods of the type Lanczos (or Krylov) that are already widely used in circuit simulations for electrothermal and electromagnetic problems. The concept of response participation factors is introduced for the selection of the trial vectors in the proposed model-reduction methods. Further, we present methods to develop simple equivalent circuit networks for the field component of the overall field-circuit system. The implementation of these equivalent circuit networks in circuit simulators is discussed. With the proposed model-reduction strategies, significant improvement on the efficiency of the generalized Falk method is illustrated for coupled field-circuit problems.

42 ENGINEERING↗
DOE OSTI2023

Stacking Faults Originating from Star-Defects in 4H-SiC

Intense efforts are currently in progress to study various sources of basal plane dislocations (BPDs) in SiC epitaxial layers. BPDs can generate Shockley-type stacking faults (SSFs) in SiC epitaxial layers, which have been shown to be associated with the degradation of power devices. This study shows that the star-shaped defect can be a source of several BPDs in the epitaxial layer. We investigate the complex microstructure of the star defect, the generation of BPDs, and expansion of SSFs using various complementary microscopy and optical techniques. We show direct evidence that star-defects can be a nucleation point of single-SSFs that can expand at the core of the defect. Newly found secondary dislocation arrays extending over a few centimeters away are found to be emanating from the primary arms of the star defect. The presence of such dislocation walls and the expansion of single-SSFs will affect the yield of numerous die on a wafer. Further understanding of the formation mechanism of stacking faults generated from star-defects as provided in this study helps understand their effect on SiC-based devices, which is crucial to assess device reliability.

36 MATERIALS SCIENCE↗
DOE OSTI2020

Improving Heat Conduction of Insulated Metal Substrate with Thermal Pyrolytic Graphite Core for SiC Power Module Packaging

TPG-core IMS concept was jointly explored in this study. Integrating high thermally conductive TPG graphite core into IMS is expected to simultaneously achieve high thermal conductivity from TPG and electrical functionalities from IMS. Nearly 2x thermal conductivity and 30% weight saving was demonstrated on TPG-core IMS compared to conventional Cu-core IMS. Significant junction temperature reduction (11°C) in steady state and power cycling was revealed by the thermal analysis as the result of improved thermal spreading in plane and through the thickness. The study also proved the manufacturability and compatibility of this TPG-core IMS structure to the existing IMS production and power module assembling. Finally, the integration of TPG and IMS paves a new packaging route to increase heat load, improve reliability, simplify module design and reduce assembling cost and number of steps.

36 MATERIALS SCIENCE↗