Single Flux Quantum-Based Digital Control of Superconducting Qubits in a Multichip Module
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75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
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Readout Noise of Digital Frequency Multiplexed TES Detectors for CUPID
The superconducting transition-edge sensor (TES) detectors have been the standard in cosmic microwave background (CMB) experiments for almost two decades and are now being adapted for use in nuclear physics, such as neutrinoless double beta decay searches. In this article, we focus on a new high-bandwidth frequency multiplexed TES readout system developed for CUPID, a neutrinoless double beta decay experiment that will replace CUORE. In order to achieve the high energy resolution requirements for CUPID, the readout noise of the system must be kept to a minimum. Low TES operating resistance and long wiring between the readout SQUID and the warm electronics are needed for CUPID, prompting a careful consideration of the design parameters of this application of frequency multiplexing. In this work, we characterize the readout noise of the newly designed frequency multiplexed TES readout system for CUPID and construct a noise model to understand it. Here, we find that current sharing between the SQUID coil impedance and other branches of the circuit, as well as the long output wiring, worsen the readout noise of the system. To meet noise requirements, a SQUID with a low input inductance, high transimpedance, and/or low dynamic impedance is needed, and the wiring capacitance should be kept as small as possible. Alternatively, the option of adding a cryogenic low-noise amplifier at the output of the SQUID should be explored.
CUPID↗
Analog-to-digital converter based on voltage-controlled superconducting devices
The increasing demand for cryogenic electronics in superconducting and quantum computing systems calls for ultra-energy-efficient data conversion architectures that remain functional at deep cryogenic temperatures. Here, in this work, we present the first design of a voltage-controlled superconducting flash analog-to-digital converter (ADC) based on a voltage-controlled quantum-enhanced Josephson junction field-effect transistor (JJFET). Exploiting its strong gate tunability and transistor-like behavior, the JJFET offers a scalable alternative to conventional current-controlled superconducting devices while aligning naturally with CMOS-style design methodologies. Building on our previously developed Verilog-A compact model calibrated to experimental data, we design and simulate a three-bit JJFET-based flash ADC targeted for integration within cryogenic control and readout circuitry in quantum computing. The core comparator block is realized through careful bias current selection and augmented with a three-terminal nanocryotron to precisely define reference voltages. Cascaded JJFET comparators ensure robust voltage gain, cascadability, and logic-level restoration across stages. Simulation results demonstrate accurate quantization behavior with ultra-low power dissipation, underscoring the feasibility of voltage-driven superconducting mixed-signal circuits. This work establishes a critical step toward unifying superconducting logic and data conversion, paving the way for scalable cryogenic architectures in quantum–classical co-processors, low-power artificial intelligence accelerators, and next-generation energy-constrained computing platforms.
Analog-to-digital converter↗
Open Circuit Switch Fault Management Method of a Multi-Phase Synchronous Buck Converter for EV Charging Application
Multi-phase synchronous buck converter (MSBC) is becoming popular for the electric vehicle (EV) charging application because of its higher efficiency, smaller passive component sizes, bidirectional power flow, and output current ripple reduction through interleaving. This converter also provides higher reliability than the traditional single phase converter since its modular structure enables fault tolerant operation. Fault management in the converter requires the detection of switch fault, shut down of the faulty phase, and reconfiguration of the PWM signals for the healthy phases to avoid circulating current and high output current ripple. In addition, it is desirable that the fault management method can be implemented using the micro-controller unit (MCU) or digital signal processor (DSP), which are widely used to control power converters. This paper presents a fault management method for detecting switch faults and reconfiguring healthy phases using a DSP. The method is validated through simulations and experiments using a commercial off-the-shelf power stack.
32 ENERGY CONSERVATION, CONSUMPTION, AND UTILIZATI↗
Accelerating computing for the future electric grid (CRADA Final Report)
As a participant in the Cyclotron Road Lab-Embedded Entrepreneurship Program (LEEP), Vellex Computing, Inc. has successfully validated the "Vellex Computing Stack," a breakthrough Analog Neural Computer (ANC) specifically designed for high-performance edge optimization. This project achieved critical milestones in mixed-signal circuit stability and software-hardware co-design, directly addressing national priorities in semiconductor resiliency. The success of this work is deeply rooted in the support from the Cyclotron Road LEEP, which provided the essential "hard tech" runway—funding, mentorship, and access to Lawrence Berkeley National Laboratory’s world-class characterization facilities—allowing Vellex to overcome the "Valley of Death" often faced by deep-tech hardware startups. By leveraging LBNL’s advanced testing infrastructure, Vellex was able to rigorously benchmark the ANC architecture against state-of-the-art digital solutions, a feat that would have been resource-prohibitive independently. This collaboration has not only advanced American leadership in analog computing but has also matured Vellex’s technology to a stage ripe for private sector commercialization.
24 POWER TRANSMISSION AND DISTRIBUTION↗
Understanding the Phase of Responsivity and Noise Sources in Frequency-Domain Multiplexed Readout of Transition Edge Sensor Bolometers
Abstract Cosmic microwave background (CMB) experiments have deployed focal planes with $$\mathcal {O}(10^{4})$$ O ( 10 4 ) transition edge sensor (TES) bolometers cooled to sub-Kelvin temperatures by multiplexing the readout of many TES channels onto a single pair of wires. Digital Frequency-domain Multiplexing (DfMux) is a multiplexing technique used in many CMB polarization experiments, such as the Simons Array, SPT-3 G, and EBEX. The DfMux system studied here uses LC filters with resonant frequencies ranging from 1.5 to 4.5 MHz connected to an array of TESs. Each detector has an amplitude-modulated carrier tone at the resonant frequency of its accompanying LC resonator. The signal is recovered via quadrature demodulation where the in-phase (I) component of the demodulated current is in phase with the complex admittance of the circuit and the quadrature (Q) component is orthogonal to I. Observed excess current noise in the Q component is consistent with fluctuations in the resonant frequency. This noise has been shown to be non-orthogonal to the phase of the detector’s responsivity. We present a detailed analysis of the phase of responsivity of the TES and noise sources in our DfMux readout system. Further, we investigate how modifications to the TES operating resistance and bias frequency can affect the phase of noise relative to the phase of the detector responsivity, using data from Simons Array to evaluate our predictions. We find that both the phase of responsivity and phase of noise are functions of the two tuning parameters, which can be purposefully selected to maximize signal-to-noise (SNR) ratio.
47 OTHER INSTRUMENTATION↗
Numerical and experimental analysis of mechanically induced failure in electric vehicle battery modules
Mitigating thermal runaway and cell-to-cell propagation is essential for improving the safety of electric and hybrid vehicles. Enhancing digital twin capabilities to predict battery mechanical abuse is particularly critical for automotive and aerospace applications, where crashworthiness is a key concern. Understanding failure conditions and propagation in battery modules during mechanical abuse is complex due to interactions between structural deformation, heat transfer, electrochemical processes, exothermic reactions and mechanical fracture. While prior studies have focused on modeling cell-level behavior, extending these models to module or pack level is necessary for a system level understating of electric vehicle safety. This study develops coupled large deformation finite element models that simultaneously solve for electrochemistry, material failure, internal short circuit and thermal runaway propagation. The models account for mechanical and thermal interactions between lithium-ion cells and other battery components while the contact interfaces are evolving with time. Model-predicted voltage, temperature and force responses are compared with experimental data for validation. The results demonstrate that the approach captures key failure mechanisms, including thermal propagation through heat transfer, electrical propagation from short circuits in parallel-connected cells, and mechanical propagation via penetration and crack formation. These findings show that computational models are valuable tools for understanding battery module failure and providing insight that can reduce the need for extensive experimental testing.
25 ENERGY STORAGE↗
Tunable stochastic memristors for energy-efficient encryption and computing
Information security and computing, two critical technological challenges for post-digital computation, pose opposing requirements – security (encryption) requires a source of unpredictability, while computing generally requires predictability. Each of these contrasting requirements presently necessitates distinct conventional Si-based hardware units with power-hungry overheads. This work demonstrates Cu 0.3 Te 0.7 /HfO 2 (‘CuTeHO’) ion-migration-driven memristors that satisfy the contrasting requirements. Under specific operating biases, CuTeHO memristors generate truly random and physically unclonable functions, while under other biases, they perform universal Boolean logic. Using these computing primitives, this work experimentally demonstrates a single system that performs cryptographic key generation, universal Boolean logic operations, and encryption/decryption. Circuit-based calculations reveal the energy and latency advantages of the CuTeHO memristors in these operations. This work illustrates the functional flexibility of memristors in implementing operations with varying component-level requirements.
97 MATHEMATICS AND COMPUTING↗
Smart Pixels: In-pixel AI for on-sensor data filtering
We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 µm\textsuperscript{2} in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e\textsuperscript{-} and a total dispersion of $\sim$100e\textsuperscript{-} The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4\% – 75.4\% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm\textsuperscript{2} staying within the experimental constraints.
Parpillon, Benjamin↗
Smart Pixels: In-pixel AI for on-sensor data filtering
We present a smart pixel prototype readout integrated circuit (ROIC) designed in CMOS 28 nm bulk process, with in-pixel implementation of an artificial intelligence (AI) / machine learning (ML) based data filtering algorithm designed as proof-of-principle for a Phase III upgrade at the Large Hadron Collider (LHC) pixel detector. The first version of the ROIC consists of two matrices of 256 smart pixels, each 25$\times$25 $\mu$m$^2$ in size. Each pixel consists of a charge-sensitive preamplifier with leakage current compensation and three auto-zero comparators for a 2-bit flash-type ADC. The frontend is capable of synchronously digitizing the sensor charge within 25 ns. Measurement results show an equivalent noise charge (ENC) of $\sim$30e$^-$ and a total dispersion of $\sim$100e$^-$ The second version of the ROIC uses a fully connected two-layer neural network (NN) to process information from a cluster of 256 pixels to determine if the pattern corresponds to highly desirable high-momentum particle tracks for selection and readout. The digital NN is embedded in-between analog signal processing regions of the 256 pixels without increasing the pixel size and is implemented as fully combinatorial digital logic to minimize power consumption and eliminate clock distribution, and is active only in the presence of an input signal. The total power consumption of the neural network is $\sim$ 300 $\mu$W. The NN performs momentum classification based on the generated cluster patterns and even with a modest momentum threshold, it is capable of 54.4% - 75.4% total data rejection, opening the possibility of using the pixel information at 40MHz for the trigger. The total power consumption of analog and digital functions per pixel is $\sim$ 6 $\mu$W per pixel, which corresponds to $\sim$ 1 W/cm$^2$ staying within the experimental constraints.
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
ASIC Scoping Study Final Report
This report documents the results and findings of a one-year scoping study investigating multichannel readout application specific integrated circuits (ASICs) for interfacing to, and processing data from, silicon photomultiplier (SiPM) arrays. We document ASIC desired and required specifications for four applications supporting national security mission areas: neutron radiography, associated particle imaging, and two versions of kinematic neutron imaging cameras. While each application has a few unique requirements that stress capability, there is generally good agreement among most. Two recently developed ASIC devices were evaluated in a system-like configuration by interfacing these to scintillator crystals exposed to gamma and neutron sources. The 64-channel ORNL device delivered functional capability while meeting most mission requirements for neutron radiography. The Nalu Scientific device, a 32-channel full waveform digitizer, did not demonstrate reliable neutron / gamma separation but it is unclear if this was an ASIC issue or problems with test setup or firmware. A literature survey of other commercial and academic ASICs was undertaken to with the conclusion that existing devices do not meet all requirements.
42 ENGINEERING↗
Solving independent set problems with photonic quantum circuits
An independent set (IS) is a set of vertices in a graph such that no edge connects any two vertices. In adiabatic quantum computation [E. Farhi, et al ., Science 292, 472–475 (2001); A. Das, B. K. Chakrabarti, Rev. Mod. Phys. 80, 1061–1081 (2008)], a given graph G ( V , E ) can be naturally mapped onto a many-body Hamiltonian H IS G ( V , E ) , with edges E being the two-body interactions between adjacent vertices V . Thus, solving the IS problem is equivalent to finding all the computational basis ground states of H IS G ( V , E ) . Very recently, non-Abelian adiabatic mixing (NAAM) has been proposed to address this task, exploiting an emergent non-Abelian gauge symmetry of H IS G ( V , E ) [B. Wu, H. Yu, F. Wilczek, Phys. Rev. A 101, 012318 (2020)]. Here, we solve a representative IS problem G ( 8 , 7 ) by simulating the NAAM digitally using a linear optical quantum network, consisting of three C-Phase gates, four deterministic two-qubit gate arrays (DGA), and ten single rotation gates. The maximum IS has been successfully identified with sufficient Trotterization steps and a carefully chosen evolution path. Remarkably, we find IS with a total probability of 0.875(16), among which the nontrivial ones have a considerable weight of about 31.4%. Our experiment demonstrates the potential advantage of NAAM for solving IS-equivalent problems.
Science & Technology - Other Topics↗
Short Circuit Detection and Voltage Sense for High Voltage Ionization Tube Power Supplies
Fermilab's PIP-II upgrade requires new rack-mounted power supplies for Beam Loss Monitor (BLM) ionization tubes compatible with the microTCA 4.1 standard, supporting high-side current measurement for short circuit detection, voltage sense telemetry, and low-side current measurement for beam loss readout. This work presents the design and preliminary schematic of such a supply. A resistive current sensing approach was chosen over inductive, optical, and Hall-effect alternatives for its independence from cable length and component availability. A 500 mΩ inline shunt steps the 2 kV common mode voltage down to roughly 70 V, producing a ~27 μV pulse during a short, which is amplified 500x, compared against a 14-bit DAC threshold, and latched to drive a fault line. Voltage sense steps the 2 kV output down at a 1V/1000V ratio, buffers it with a low bias current amplifier, and digitizes it via a 24-bit ADC over SPI. Onboard power is regulated from 12 V down to isolated 5 V and 3.3 V rails, with capacitive isolation on FPGA communication lines. Lumped parameter models were developed for the ionization tube (0.327 nF, 20 to 200 GΩ dynamic resistance) and the RG-58 coaxial cable to support the design. Component selection is complete and a preliminary schematic has been drawn in Altium Designer, forming the foundation for future prototyping and validation.
Yu, Kellen [Cornell U.]↗
Quantum computer-enabled receivers for optical communication
Abstract Optical communication is the standard for high-bandwidth information transfer in today’s digital age. The increasing demand for bandwidth has led to the maturation of coherent transceivers that use phase- and amplitude-modulated optical signals to encode more bits of information per transmitted pulse. Such encoding schemes achieve higher information density, but also require more complicated receivers to discriminate the signaling states. In fact, achieving the ultimate limit of optical communication capacity, especially in the low light regime, requires coherent joint detection of multiple pulses. Despite their superiority, such joint detection receivers are not in widespread use because of the difficulty of constructing them in the optical domain. In this work we describe how optomechanical transduction of phase information from coherent optical pulses to superconducting qubit states followed by the execution of trained short-depth variational quantum circuits can perform joint detection of communication codewords with error probabilities that surpass all classical, individual pulse detection receivers. Importantly, we utilize a model of optomechanical transduction that captures non-idealities such as thermal noise and loss in order to understand the transduction performance necessary to achieve a quantum advantage with such a scheme. We also execute the trained variational circuits on an IBM-Q device with the modeled transduced states as input to demonstrate that a quantum advantage is possible even with current levels of quantum computing hardware noise.
97 MATHEMATICS AND COMPUTING↗
Upgrade of the helically symmetric experiment Thomson scattering diagnostic suite
The Helically Symmetric eXperiment (HSX) Thomson Scattering (TS) diagnostic is being upgraded to decrease uncertainty in electron temperature and density measurements. Upgrades to the HSX TS diagnostic will consist of a novel redesign of polychromator electronics and digitization of the TS output signal. Here, we also present a study of the benefits of an additional spectral channel that will sample the red-shifted band of the scattered spectrum. In conclusion, to maximize system bandwidth (BW) and gain, while minimizing noise, the existing low-BW polychromator electronics on HSX will be replaced by high-BW, high gain circuitry designed in-house.
47 OTHER INSTRUMENTATION↗
A Cryogenic readout integrated circuit with analog pile-up and in-Pixel ADC for high frame rate Skipper CCD-in-CMOS Sensors
The Skipper CCD-in-CMOS Parallel Read-Out Circuit V2 (SPROCKET2) is designed to enable high frame rate readout of Skipper CCD-in-CMOS image sensors. The SPROCKET2 pixel is fabricated in a 65 nm CMOS process and occupies a 60$\mu$m $\times$ 60$\mu$m footprint. SPROCKET2 is intended to be heterogeneously integrated with a pixelated Skipper CCD-in-CMOS sensor, such that one readout pixel is connected to a multiplexed array of 16 active image sensor pixels, to match their spatial geometry. Our design benefits from the Skipper CCD-in-CMOS sensor's non-destructive readout capability to achieve exceptionally low noise through multi-sampling and averaging while optimizing for total power consumption. The pixel readout utilizes correlated double sampling to minimize 1/f noise and includes "pile-up" of ten successive samples in the analog domain before digitizing at a rate of 66.7 ksps. Measurement results of in-pixel serial SAR ADC show DNL and INL of ~0. 44 LSB and 0.58 LBS respectively. A large area array of 20,000 SPROCKET2 ADC pixels (multiplexed 1:16 to 320,000 sensor pixels) is currently under test. By reading out data over a 10 Gbps optical link, this pixel design enables a frame rate of $\sim$ 4 kfps for large sensing areas with minimal sensing deadtime. In the highest gain mode, the pixelated ADC has an input-referred resolution of 10$\mu$V with a simulated power consumption of 50$\mu$W. The pixel operates with constant current draw to minimize power-rail crosstalk.
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
Signal processing to reduce dark noise impact in precision timing
We introduce a technique to mitigate the effects of low frequency noise on precision timing. The example of Dark Count Noise Rate (DCR) in Silicon Photomultipliers (SiPMs) is emphasized. This technique exploits the correlation between time shifts on the leading edge of a signal and the residual slope of the baseline (due to noise) which remains after baseline subtraction. In fast timing applications (such as for Time-of-flight particle ID) the signal arrival time is typically captured on the signal leading edge. The signal risetime is often fixed by the physics of the sensor and input circuit. Then accurate pulse timing can be achieved by correcting a leading edge threshold time (depending on a slope proportional to both the Amplitude and the risetime) to a “constant fraction” time. This compensation for time walk due to amplitude fluctuations breaks down once we introduce interference from low frequency noise on the leading edge. In this paper we demonstrate that an additional measurement of the slope at threshold can be used to correct for this noise jitter.
46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
Design and Optimization of a Gas-Cooled, Airfoil Fin Microchannel Heat Exchanger
High-performance microchannel heat exchangers are needed to supply heat for power conversion for nuclear microreactors. An airfoil fin microchannel design, constructed of Alloy 617 with helium as the working fluid, was analyzed and optimized using a design of experiments with artificial intelligence and machine learning techniques. The use of airfoil fins offers the potential to reduce pressure drop across the heat exchanger, as compared to other types of channel configurations. A framework for topology optimization of airfoil fin PCHEs has been developed that can be readily extended to different fin sizes and shapes, as well as different inlet and operating conditions, materials of construction, and working fluids. An optimization procedure was developed that employs computational fluid dynamics for a set of design points identified using Latin hypercube sampling. STAR-CCM+ was used to analyze a simplified two-channel configuration where five parameters were varied – inlet angle, fin scale, extent of staggering, transverse and longitudinal pitches. Two methods were compared for generating surrogate models – a 5D polynomial and a regression neural network. A response surface approximation was created from the surrogate models and input to a genetic algorithm. The genetic algorithm identified a set of optimal points on the Pareto front. The optimal geometry was found across six channel Reynolds numbers ranging from 1000 to 5000 to analyze how varying inlet conditions affects the optimal design. A set of optimal designs that maximizes heat transfer and minimizes pressure drop was identified, and a thermal stress analysis was performed on the optimal design. This work has developed a digital framework for the expedient topology design and evaluation of PCHE designs for gas-cooled microreactor applications. Correlations for the Nusselt number and Darcy friction factor were developed that can be useful for thermal hydraulic analyses using system codes. A thermal stress analysis was conducted and a brief discussion of the status of code cases of PCHEs for nuclear applications is given. Testing and thermomechanical modeling is needed to facilitate future code compliance of PCHEs for high pressure and high temperature applications.
42 ENGINEERING↗