Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “Digital circuits”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 199 records · Page 11
All sourcesNASA NTRSDOE OSTI
NASA NTRS1987

Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications

Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMIC's to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMIC's is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

Connolly, Denis J.↗
NASA NTRS2001

Micromachined TWTs for THz Radiation Sources

The Terahertz (THz) region of the electromagnetic spectrum (about 300 - 3000 GHz in frequency or about 0.1 - 1 mm free space wavelength) has enormous potential for high-data-rate communications, spectroscopy, astronomy, space research, medicine, biology, surveillance, remote sensing, industrial process control, etc. It has been characterized as the most scientifically rich, yet under-utilized, region of the electromagnetic spectrum. The most critical roadblock to full exploitation of the THz band is lack of coherent radiation sources that are powerful (0.001 - 1.0 W continuous wave), efficient (> 1%), frequency agile (instantaneously tunable over 1% bandwidths or more), reliable, and comparatively inexpensive. To develop vacuum electron device (VED) radiation sources satisfying these requirements, fabrication and packaging approaches must be heavily considered to minimize costs, in addition to the basic interaction physics and circuit design. To minimize size of the prime power supply, beam voltage must be minimized, preferably 10 kV. Solid state sources satisfy the low voltage requirement, but are many orders of magnitude below power, efficiency, and bandwidth requirements. On the other hand, typical fast-wave VED sources in this regime (e.g., gyrotrons, FELs) tend to be large, expensive, high voltage and very high power devices unsuitable for most of the applications cited above. VEDs based on grating or inter-digital (ID) circuits have been researched and developed. However, achieving forward-wave amplifier operation with instantaneous fractional bandwidths > 1% is problematic for these devices with low-energy (< 15 kV) electron beams. Moreover, the interaction impedance is quite low unless the beam-circuit spacing is kept particularly narrow, often leading to significant beam interception. One solution to satisfy the THz source requirements mentioned above is to develop micromachined VEDs, or "micro-VEDs". Among other benefits, micro-machining technologies provide superior high frequency wall conductivity as a result of superior surface smoothness compared with conventional mechanical or electric discharge machining approaches. Micro-VED technologies are already being applied to the development of millimeter-wave klystrons at Stanford Linear Accelerator Center and submillimeter-wave klystrons at the University of Leeds. We are investigating the use of micro-machining technologies to develop THz regime TWTs, with emphasis on folded-waveguide TWTs. The folded-waveguide TWT (FW-TWT) has several features that make it attractive for THz-regime micro-VED applications. It is a relatively simple circuit to design and fabricate, it is amenable to precision pattern replication by micro-machining, and it is has been demonstrated capable of forward-wave amplification with appreciable bandwidth. We are conducting experimental and computational studies of micro-VED FW-TWTs to examine their feasibility for applications at frequencies from 200 - 1000 GHz.

Booske, John H.↗
NASA NTRS2000

Digital Channel Simulator Developed and Tested

The Digital Channel Simulator (DCS) is a real-time test set developed in-house by the NASA Glenn Research Center at Lewis Field that simulates the characteristics of the modulator, demodulator, and transmission medium in a typical communications system to enable controlled laboratory testing of codec pairs. The DCS can support data rates up to 100 megasymbols per second (Msymbols/sec) with symbol sizes up to 10 bits and is compatible with both TTL (transistor transistor logic) and ECL (emitter coupled logic) interfaces. Because of its use of digital integrated circuits (IC's), the DCS offers the user accurate and repeatable testing while maintaining a simple reconfiguration of the modulation scheme and noise characteristics. The PC-based graphical user interface (GUI) assures user friendly operation for configuring, controlling, and monitoring the DCS and system during tests. In a typical communications system, the modulator places a symbol in constellation space and puts it on a carrier to be sent to the demodulator. Because of noise on the channel, the I and Q position in constellation space cannot be recovered exactly, and the received coordinates shift. To mimic this process in the laboratory, the DCS uses a mapper to place the symbol in constellation space. It simulates the shift in coordinates by digitally adding "noise" to the I and Q values. The mapper and noise source are implemented in lookup tables. Modulation schemes and noise characteristics are set by the values loaded in these tables. The mapper also has a pass-through mode to facilitate modulator testing, allowing noise to be added to 8-bit I and Q values of modulated data without a second mapping. To achieve high symbol rates, eight processing circuits are placed in parallel between an ECL demultiplexer and multiplexer. A graphical user interface was developed to calculate, load, and verify the values for the lookup tables. This interface can also be used to debug and verify proper operation of the channel simulator or to control an experiment. Operation of the DCS has been verified through three tests: a low-speed comprehensive system test, a high-speed (20 Msymbols/sec) test of the TTL interface, and a high-speed (100 Msymbols/sec) test of the ECL interface. The DCS is now ready for use by NASA and external customers.

Bizon, Thomas P.↗
NASA NTRS1989

Advanced technology satellite demodulator development

Ford Aerospace has developed a proof-of-concept satellite 8 phase shift keying (PSK) modulation and coding system operating in the Time Division Multiple Access (TDMA) mode at a data range of 200 Mbps using rate 5/6 forward error correction coding. The 80 Msps 8 PSK modem was developed in a mostly digital form and is amenable to an ASIC realization in the next phase of development. The codec was developed as a paper design only. The power efficiency goal was to be within 2 dB of theoretical at a bit error rate (BER) of 5x10(exp 7) while the measured implementation loss was 4.5 dB. The bandwidth efficiency goal was 2 bits/sec/Hz while the realized bandwidth efficiency was 1.8 bits/sec/Hz. The burst format used a preamble of only 40 8 PSK symbol times including 32 symbols of all zeros and an eight symbol unique word. The modem and associated special test equipment (STE) were fabricated mostly on a specially designed stitch-weld board although a few of the highest rate circuits were built on printed circuit cards. All the digital circuits were ECL to support the clock rates of from 80 MHz to 360 MHz. The transmitter and receiver matched filters were square-root Nyquist bandpass filters realized at the 3.37 GHz i.f. The modem operated as a coherent system although no analog phase locked (PLL) loop was employed. Within the budgetary constraints of the program, the approach to the demodulator has been proven and is eligible to proceed to the next phase of development of a satellite demodulator engineering model. This would entail the development of an ASIC version of the digital portion of the demodulator, and MMIC version of the quadrature detector, and SAW Nyquist filters to realize the bandwidth efficiency.

Ames, Stephen A.↗
NASA NTRS2004

Digital Radar-Signal Processors Implemented in FPGAs

High-performance digital electronic circuits for onboard processing of return signals in an airborne precipitation- measuring radar system have been implemented in commercially available field-programmable gate arrays (FPGAs). Previously, it was standard practice to downlink the radar-return data to a ground station for postprocessing a costly practice that prevents the nearly-real-time use of the data for automated targeting. In principle, the onboard processing could be performed by a system of about 20 personal- computer-type microprocessors; relative to such a system, the present FPGA-based processor is much smaller and consumes much less power. Alternatively, the onboard processing could be performed by an application-specific integrated circuit (ASIC), but in comparison with an ASIC implementation, the present FPGA implementation offers the advantages of (1) greater flexibility for research applications like the present one and (2) lower cost in the small production volumes typical of research applications. The generation and processing of signals in the airborne precipitation measuring radar system in question involves the following especially notable steps: The system utilizes a total of four channels two carrier frequencies and two polarizations at each frequency. The system uses pulse compression: that is, the transmitted pulse is spread out in time and the received echo of the pulse is processed with a matched filter to despread it. The return signal is band-limited and digitally demodulated to a complex baseband signal that, for each pulse, comprises a large number of samples. Each complex pair of samples (denoted a range gate in radar terminology) is associated with a numerical index that corresponds to a specific time offset from the beginning of the radar pulse, so that each such pair represents the energy reflected from a specific range. This energy and the average echo power are computed. The phase of each range bin is compared to the previous echo by complex conjugate multiplication to obtain the mean Doppler shift (and hence the mean and variance of the velocity of precipitation) of the echo at that range.

Berkun, Andrew↗
NASA NTRS1990

Path programmable logic: A structured design method for digital and/or mixed analog integrated circuits

The design of Integrated Circuits has evolved past the black art practiced by a few semiconductor companies to a world wide community of users. This was basically accomplished by the development of computer aided design tools which were made available to this community. As the tools matured into different components of the design task they were accepted into the community at large. However, the next step in this evolution is being ignored by the large tool vendors hindering the continuation of this process. With system level definition and simulation through the logic specification well understood, why is the physical generation so blatantly ignored. This portion of the development is still treated as an isolated task with information being passed from the designer to the layout function. Some form of result given back but it severely lacks full definition of what has transpired. The level of integration in I.C.'s for tomorrow, whether through new processes or applications will require higher speeds, increased transistor density, and non-digital performance which can only be achieved through attention to the physical implementation.

Taylor, B.↗
NASA NTRS1984

Optimum Cyclic Redundancy Codes for Noisier Channels

Binary cyclic redundancy codes for feedback communication over noisy digital links are considered. The standard 16 bit American Data and Computer Communication Protocol (ADCCP) polynomial is designed for digital links which already have a low input bit error probability. For file transfer between personal computers over telephone circuits, the quality of resulting digital circuit may be much lower. The 3 byte (24 bit) and 4 byte (32 bit) polynomials are considered. Generator polynomials of a certain class have minimum weight and yet achieve the bound on minimum distance for arbitrary codes. Particular choices for 24 bit and 32 bit redundancies are exhibited: of weight and distance 6 in the 24-bit case; and weight 10 and distance 8 in the 32-bit case.

Merkey, P.↗
NASA NTRS1984

Optimum cyclic redundancy codes for noisy channels

Binary cyclic redundancy codes for feedback communication over noisy digital links are considered. The standard 16 bit American Data and Computer Communication Protocol (ADCCP) polynomial is designed for digital links which already have a low input bit error probability. For file transfer between personal computers over telephone circuits, the quality of resulting digital circuit may be much lower. The 3 byte (24 bit) and 4 byte (32 bit) polynomials are considered. Generator polynomials of a certain class have minimum weight and yet achieve the bound on minimum distance for arbitrary codes. Particular choices for 24 bit and 32 bit redundancies are exhibited: of weight and distance 6 in the 24-bit case; and weight 10 and distance 8 in the 32-bit case.

Merkey, P.↗
NASA NTRS1966

New television camera eliminates vidicon tube

Small, lightweight camera systems use solid state imaging devices in the form of phototransistor mosaic sensors instead of vidicon tubes for light sensing and image conversion. The digital logic circuits scan the sensor mosaic at 60 frames per second to produce pictures composed of a series of dots rather than lines.

Source record↗
NASA NTRS1966

Solid-state switch increases switching speed

Solid state switch for commutating capacitors in an RC commutated network increases switching speed and extends the filtering or commutating frequency spectrum well into the kilocycle region. The switch is equivalent to the standard double- pole double-throw /DPDT/ relay and is driven from digital micrologic circuits.

Mc~gowan, G. F.↗
NASA NTRS1967

Program computes single-point failures in critical system designs

Computer program analyzes the designs of critical systems that will either prove the design is free of single-point failures or detect each member of the population of single-point failures inherent in a system design. This program should find application in the checkout of redundant circuits and digital systems.

Brown, W. R.↗
NASA NTRS1966

Advanced test techniques

Voltage margin tests, infrared scanning, and RF NOISE spectra measurements for digital test circuits

INFRARED SCANNER↗
NASA NTRS1971

Efficient digital comparison technique for logic circuits

Tolerance compare technique indicates discompare only when numerical difference value exceeds prescribed limit. Algorithm involving binary number properties is defined, in lieu of arithmetic operation which requires relatively complex circuitry. Extension of algorithm may be made to encompass tolerances other than one unit.

Mccarthy, C. E.↗