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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Radiation hardened/tolerant Active Pixel Sensor CMOS imagers that can be adaptively windowed with low power, on-chip control, timing, digital output and provide data-channel efficient on-chip compression, high bandwidth optical communications links are being designed and investigated to reduce size, weight and cost for common optics/hybrid architectures.
This document serves as the fiscal year end report for the NEPP scaled complementary metal-oxide semiconductor (CMOS) task. Much of the effort this year focused on development of test capability and initial collection of data on SDRAM devices. Since the system has only just begun (in the last four weeks) to gather data, this report focuses on the test system and preliminary results.
Low dose rate (LDR) and high dose rate (HDR) experiments on field-oxide-field-effect-transistors (FOXFETs) and gated lateral pnp (GLPNP) bipolar transistors indicate that there is a dose rate enhancement factor (EF) associated with radiation-induced degradation. This EF is also affect by the presence of hydrogen in the oxide. In this work, we developed a one dimensional (1-D) numerical calculations code to investigate the key mechanisms that describe the dose rate sensitivity and the effect of hydrogen on dose rate effects. We used a finite-difference methodology for the numerical calculations that allow for computing solutions for the densities of the mobile species as well as for the electrostatic potential at nodes contained within a mesh superimposed on the solution domain. Results from calculations of damage EF indicate that oxide thickness, distribution of hole traps and hole capture cross-section affect dose rate sensitivity. In addition, calculations show that molecular hydrogen cracking at positively charged defects may be a key reaction relating hydrogen and dose rate response. Comparison to experimental data on bipolar and CMOS devices results in good agreement with the dose rate calculations of interface trap buildup
A fully integrated CMOS THz transmitter for short range data-links is presented which provides 0.47 mW of output power to 294 GHz. The output frequency is derived from a 147 GHz on-chip LO and fully differential caterpillar power amplifier combined with a transformer coupled frequency doubler. The transmitter is integrated with an on-chip dipole antenna for use in THz communication systems and consumes a total of 258 mW.
This paper presents a dual-loop chip-scale molecular clock (CSMC), which enhances the Allan Deviation performance by combining high signal-to-noise ratio of using fundamental mode and long-term stability of using higher order modes in derivative molecular absorption spectroscopy. In addition, digital frequency-error integration is adopted in the frequency-locked loop to provide an infinite open-loop DC gain, which fully suppresses any frequency drift caused by the temperature-sensitive crystal oscillator. This new generation CSMC is implemented in 65-nm CMOS, and achieves 20 ppt (part-per-trillion) Allan Deviation at 10,000 s averaging time with 71-mW power consumption.
We develop guidelines for a priori assessment of risk due to potentially SEL susceptible parts by exploratory analysis of large datasets of SEL test data for unhardened CMOS parts.
SEL is a serious obstacle to use of state-of-the-art microelectronics, and a priori prediction of SEL susceptibility has proven elusive. We develop SEL risk-assessment tools based on analysis of large archives of SEL test data for unhardened CMOS parts. Results include a flexible method for bounding SEL rates even with minimal test data.
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This paper discusses single-event upset in memories and microprocessors, along with the mechanisms that cause SEU effects.
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A highly integrated active pixel sensor with on-chip 1 bit thresholding circuitry achieving an 8,000.
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JPL, under sponsorship from the NASA Office of Advanced Concepts and Technology, has been developing a second-generation solid-state image sensor technology. Charge-coupled devices (CCD) are a well-established first generation image sensor technology. For both commercial and NASA applications, CCDs have numerous shortcomings. In response, the active pixel sensor (APS) technology has been under research. The major advantages of APS technology are the ability to integrate on-chip timing, control, signal-processing and analog-to-digital converter functions, reduced sensitivity to radiation effects, low power operation, and random access readout.
Heavy-ion latchup is investigated for analog-to-digital converters. Differences in cross section for various ions shows that charge is collected at depths beyond 50 um, causing the cross section to be underestimated unless long-range ions are used. Current distributions and thermal imaging were used to identify latchup-sensitive regions. Latchup in one of the circuittypes was catastrophic, even when the power was turned off within 10 ms of a latchup event.
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