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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 199 records · Page 11
All sourcesNASA NTRSDOE OSTI
NASA NTRS2010

Analysis of Weibull Grading Test for Solid Tantalum Capacitors

Weibull grading test is a powerful technique that allows selection and reliability rating of solid tantalum capacitors for military and space applications. However, inaccuracies in the existing method and non-adequate acceleration factors can result in significant, up to three orders of magnitude, errors in the calculated failure rate of capacitors. This paper analyzes deficiencies of the existing technique and recommends more accurate method of calculations. A physical model presenting failures of tantalum capacitors as time-dependent-dielectric-breakdown is used to determine voltage and temperature acceleration factors and select adequate Weibull grading test conditions. This, model is verified by highly accelerated life testing (HALT) at different temperature and voltage conditions for three types of solid chip tantalum capacitors. It is shown that parameters of the model and acceleration factors can be calculated using a general log-linear relationship for the characteristic life with two stress levels.

Teverovsky, Alexander↗
NASA NTRS2017

Reliability Issues with PME and BME Ceramic Capacitors

This work is a review of reliability issues specific for low-voltage precious metal electrode (PME) and base metal electrode (BME) multilayer ceramic capacitors (MLCC). A special attention is given to degradation and failures in capacitors with defects, in particular with cracks. Temperature and voltage reliability acceleration factors have been calculated based on approximation of distributions of degradation rates of leakage currents using a general log-linear Weibull model. Results show a substantial difference in behavior of BME and PME capacitors with defects. Mechanisms of degradation and failures in humid and dry environments and risks of overstressing capacitors during highly accelerated life testing (HALT) are discussed.

Teverovsky, Alexander↗
NASA NTRS2008

Effects of hand soldering MIL-PRF 55365 tantalum capacitors

Different values of MIL-PRF-55365 tantalum capacitors were subjected to three different types of soldering conditions— Convection Reflow, JPL Standard Hand Soldering, and Optimized Hand Soldering. The electrical parameters for a large number of capacitors of each value were measured before and after thermal soldering stress. The results indicate that tantalum capacitors subjected to convection reflow conditions experience detectable changes in electrical parameters; capacitors subjected to hand solder conditions show reduced changes in electrical parameters when compared to the reflow samples. Optimized hand solder conditions are shown to have a minimal effect on electrical parameters.

Sheldon, Douglas↗
NASA NTRS2020

An embedded planar-foil capacitor material, FPGA based interposer, aimed at improving system performance and reduced board size for space based electronics

This paper presents work to date in developing, and testing an embedded planar-foil capacitor based interposer intended to be integrated together with high-density components such as Field Programmable Gate Arrays (FPGAs), and Application Specific Integrated Circuits (ASIC). FPGA devices typically have a large number of I/O and power pins. The high speed enabled by these devices requires a large number of discrete bypass capacitors as close as possible to the power pins. These capacitors take up a considerable amount of the board area on the application circuit board. The developed interposer replaces these components freeing up space of traditional bypass capacitors for other circuitry.

Cheng, Ben↗
NASA NTRSDate not supplied

Evaluation of Feed-Through Polymer Tantalum Capacitors for Space Applications

In 2023 AVX developed a new technology of feed-through capacitors that can be used for high (up to GHz range) frequency signal filtering for FPGA, microswitches or micro-DC-DC converters as a replacement for the currently used MLCCs. This part is a Low Inductance Bulk Capacitor (LIBC). It has low ESR and insertion loss values and is manufactured using technology similar to chip polymer tantalum capacitors and have. The purpose of this work is to evaluate the design and performance of the parts using engineering samples from AVX, address potential reliability issues, and suggest screening and lot acceptance procedures necessary to use these capacitors in space projects.

Alexander Teverovsky↗
DOE OSTI2017

Method of making dielectric capacitors with increased dielectric breakdown strength

The invention is directed to a process for making a dielectric ceramic film capacitor and the ceramic dielectric laminated capacitor formed therefrom, the dielectric ceramic film capacitors having increased dielectric breakdown strength. The invention increases breakdown strength by embedding a conductive oxide layer between electrode layers within the dielectric layer of the capacitors. The conductive oxide layer redistributes and dissipates charge, thus mitigating charge concentration and micro fractures formed within the dielectric by electric fields.

36 MATERIALS SCIENCE↗
DOE OSTI2019

Carbon fiber and parylene structural capacitor

A structural capacitor and method for manufacturing the structural capacitor. A first layer of nonconductive fiber glass may be formed into a desired shape of the structural capacitor, and then a conductive layer made of carbon fiber pre-impregnated material may be placed on the fiber glass layer. A dielectric layer of parylene may then be coated onto the conductive layer using a conformal vapor deposition process. More conductive and dielectric layers may be added in alternating succession until desired structural and/or electrical properties are achieved. A final layer of fiber glass may then be applied and the resulting structural capacitor may be cured.

36 MATERIALS SCIENCE↗
DOE OSTI2019

Submodule Capacitor Reduction for a 1 MVA SiC-Based Modular Multilevel Converter Motor Drive using High Frequency Common-Mode Voltage Injection

This paper describes a strategy to reduce the size of submodule capacitors of a 1 MVA, 0-1 kHz, 7-level modular multilevel converter (MMC) based medium voltage variable speed drive (MVVSD) using 1.7 kV SiC MOSFETs. Hardware designs of submodules to withstand high dv/dt and capacitor selection based on common mode voltage injection have been presented in literature. The issue with injection is the error in tracking of injected circulation current which results in fundamental frequency fluctuations in the submodule capacitor voltage. This paper presents a strategy for higher frequency sinusoidal common mode voltage based on more accurate tracking of the circulating current; realized through an improved control strategy combined with a higher switching frequency. Using the methods presented in this paper, a smaller submodule capacitance and reduced output current THD of the motor drive is achieved. A loss analysis model is proposed to evaluate the effect of the proposed strategy on the MMC efficiency. This helps balance the reduction in the capacitor against the increase in the losses as a result of increased switching frequency. Simulations and a down-scaled experimental setup are used to demonstrate this concept.

Potty, Karun↗
DOE OSTI2014

A new time calibration method for switched-capacitor-array-based waveform samplers

Here we have developed a new time calibration method for the DRS4 waveform sampler that enables us to precisely measure the non-uniform sampling interval inherent in the switched-capacitor cells of the DRS4. The method uses the proportionality between the differential amplitude and sampling interval of adjacent switched-capacitor cells responding to a sawtooth-shape pulse. In the experiment, a sawtooth-shape pulse with a 40 ns period generated by a Tektronix AWG7102 is fed to a DRS4 evaluation board for calibrating the sampling intervals of all 1024 cells individually. The electronic time resolution of the DRS4 evaluation board with the new time calibration is measured to be ~2.4 ps RMS by using two simultaneous Gaussian pulses with 2.35 ns full-width at half-maximum and applying a Gaussian fit. The time resolution dependencies on the time difference with the new time calibration are measured and compared to results obtained by another method. Ultimately, the new method could be applicable for other switched-capacitor-array technology-based waveform samplers for precise time calibration.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2018

Design of Near Infrared and Visible Kinetic Inductance Detectors Using MIM Capacitors

We are developing superconducting Microwave Kinetic Inductance Detectors to operate at near infrared and optical wavelengths for astronomy. In order to efficiently meet with the requirements of astronomical applications, we propose to replace the interdigitated capacitor by a metal–insulator–metal capacitor which has the advantage of presenting a larger capacitance value within a much smaller space. The pixel will occupy a space of typically 100 × 85 µm which is nine times less than a typical pixel size using the interdigitated capacitor operating at the same frequency, below 2 GHz.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2015

Impact of total ionizing dose irradiation on Pt/SrBi{sub 2}Ta{sub 2}O{sub 9}/HfTaO/Si memory capacitors

In this work, metal-ferroelectric-insulator-semiconductor (MFIS) structure capacitors with SrBi{sub 2}Ta{sub 2}O{sub 9} (300 nm) as ferroelectric thin film and HfTaO (6 nm, 8 nm, 10 nm, and 12 nm) as insulating buffer layer were proposed and investigated. The prepared capacitors were fabricated and characterized before radiation and then subjected to {sup 60}Co gamma irradiation in steps of two dose levels. Significant irradiation-induced degradation of the electrical characteristics was observed. The radiation experimental results indicated that stability and reliability of as-fabricated MFIS capacitors for nonvolatile memory applications could become uncontrollable under strong irradiation dose and/or long irradiation time.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2015

Simulation of electron transmittance and tunnel current in n{sup +} Poly-Si/HfSiO{sub x}N/Trap/SiO{sub 2}/Si(100) capacitors using analytical and numerical approaches

In this paper, we discuss the electron transmittance and tunneling current in high-k-based-MOS capacitors with trapping charge by including the off-diagonal effective-mass tensor elements and the effect of coupling between transverse and longitudinal energies represented by an electron velocity in the gate. The HfSiO{sub x}N/SiO{sub 2} dual ultrathin layer is used as the gate oxide in an n{sup +} poly- Si/oxide/Si capacitor to replace SiO{sub 2}. The main problem of using HfSiO{sub x}N is the charge trapping formed at the HfSiO{sub x}N/SiO{sub 2} interface that can influence the performance of the device. Therefore, it is important to develop a model taking into account the presence of electron traps at the HfSiO{sub x}N/SiO{sub 2} interface in the electron transmittance and tunneling current. The transmittance and tunneling current in n{sup +} poly- Si/HfSiO{sub x}N/trap/SiO2/Si(100) capacitors are calculated by using Airy wavefunctions and a transfer matrix method (TMM) as analytical and numerical approaches, respectively. The transmittance and tunneling current obtained from the Airy wavefunction are compared to those computed by the TMM. The effects of the electron velocity on the transmittance and tunneling current are also discussed.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2016

Iodine encapsulation in CNTs and its application for electrochemical capacitor

We report the experimental results for new type electrochemical capacitor using iodine redox reaction in single-walled carbon nanotubes (SWCNTs). It was found that the energy density of the present redox capacitor using SWCNTs is almost three times larger than that of the normal electric double layer capacitor.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2016

Fabrication of PVDF-TrFE based bilayered PbTiO{sub 3}/PVDF-TrFE films capacitor

Development of high performance capacitor is reaching towards new generation where the ferroelectric materials take places as the active dielectric layer. The motivation of this study is to produce high capacitance device with long life cycle. This was configured by preparing bilayered films where lead titanate as an active dielectric layer and stacked with the top dielectric layer, poly(vinyledenefluoride-trifluoroethylene). Both of them are being referred that have one in common which is ferroelectric behavior. Therefore the combination of ceramic and polymer ferroelectric material could perform optimum dielectric characteristic for capacitor applications. The fabrication was done by simple sol-gel spin coating method that being varied at spinning speed property for polymer layers, whereas maintaining the ceramic layer. The characterization of PVDF-TrFE/PbTiO3 was performed according to metal-insulator-metal stacked capacitor measurement which includes structural, dielectric, and ferroelectric measurement.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2016

High capacitance density MIS capacitor using Si nanowires by MACE and ALD alumina dielectric

High capacitance density three-dimensional (3D) metal-insulator-semiconductor (MIS) capacitors using Si nanowires (SiNWs) by metal-assisted chemical etching and atomic-layer-deposited alumina dielectric film were fabricated and electrically characterized. A chemical treatment was used to remove structural defects from the nanowire surface, in order to reduce the density of interface traps at the Al{sub 2}O{sub 3}/SiNW interface. SiNWs with two different lengths, namely, 1.3 μm and 2.4 μm, were studied. A four-fold capacitance density increase compared to a planar reference capacitor was achieved with the 1.3 μm SiNWs. In the case of the 2.4 μm SiNWs this increase was ×7, reaching a value of 4.1 μF/cm{sup 2}. Capacitance-voltage (C-V) measurements revealed that, following a two-cycle chemical treatment, frequency dispersion at accumulation regime and flat-band voltage shift disappeared in the case of the 1.3 μm SiNWs, which is indicative of effective removal of structural defects at the SiNW surface. In the case of the 2.4 μm SiNWs, frequency dispersion at accumulation persisted even after the two-step chemical treatment. This is attributed to a porous Si layer at the SiNW tops, which is not effectively removed by the chemical treatment. The electrical losses of MIS capacitors in both cases of SiNW lengths were studied and will be discussed.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2016

GeO{sub x} interfacial layer scavenging remotely induced by metal electrode in metal/HfO{sub 2}/GeO{sub x}/Ge capacitors

The metal gate electrodes of Ni, W, and Pt have been investigated for their scavenging effect: a reduction of the GeO{sub x} interfacial layer (IL) between HfO{sub 2} dielectric and Ge substrate in metal/HfO{sub 2}/GeO{sub x}/Ge capacitors. All the capacitors were fabricated using the same process except for the material used in the metal electrodes. Capacitance-voltage measurements, scanning transmission electron microscopy, and electron energy loss spectroscopy were conducted to confirm the scavenging of GeO{sub x} IL. Interestingly, these metals are observed to remotely scavenge the interfacial layer, reducing its thickness in the order of Ni, W, and then Pt. The capacitance equivalent thickness of these capacitors with Ni, W, and Pt electrodes are evaluated to be 2.7 nm, 3.0 nm, and 3.5 nm, and each final remnant physical thickness of GeO{sub x} IL layer is 1.1 nm 1.4 nm, and 1.9 nm, respectively. It is suggested that the scavenging effect induced by the metal electrodes is related to the concentration of oxygen vacancies generated by oxidation reaction at the metal/HfO{sub 2} interface.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2015

Metal-HfO{sub 2}-Ge capacitor: Its enhanced charge trapping properties with S-treated substrate and atomic-layer-deposited HfO{sub 2} layer

The charge trapping properties of metal-HfO{sub 2}-Ge capacitor as a nonvolatile memory have been investigated with (NH{sub 4}){sub 2}S-treated Ge substrate and atomic-layer-deposited HfO{sub 2} layer. The interfacial layer generated by (NH{sub 4}){sub 2}S-treated Ge substrate reveals a trace of -S- bonding, very sharp interface edges, and smooth surface morphology. The Ru-HfO{sub 2}-Ge capacitor with (NH{sub 4}){sub 2}S-treated Ge substrate shows an enhanced interface state with little frequency dispersion, a lower leakage current, and very reliable properties with the enhanced endurance and retention than Ru-HfO{sub 2}-Ge capacitor with cyclic-cleaned Ge substrate.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2025

DC-Link Capacitor Design for a Neutral-Point-Less Three-Level Dual-Phase Inverter for Traction Application

Conventional multilevel inverters, such as neutral￾point-clamped and T-type inverters, have gained popularity in electric vehicle applications due to their advantages, including high voltage range, high power capability, low switching losses, low total harmonic distortion, and low electromagnetic interference. However, these traditional multilevel inverters require a neutral point connection to generate a zero-voltage vector. The neutral point current oscillates at three times the fundamental frequency, leading to voltage imbalance and overvoltage stress on the power modules. Additionally, the use of two stacked DC-link capacitors increases the volume required for the same overall capacitance and complicates packaging due to ripple current and heat dissipation from separate components. This is a significant concern for traction drive units, where space is limited. In this paper, a neutral-point-less multilevel dual three￾phase inverter topology is investigated for traction inverter applications. Simulation results demonstrate that the proposed topology effectively retains the benefits of multilevel operation while utilizing a single DC-link capacitor. The inverter model was simulated in conjunction with an industry-standard battery model to evaluate the potential for capacitor size reduction compared to a conventional three-level inverter.

33 ADVANCED PROPULSION SYSTEMS↗