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The measured propagation constant of a coplanar waveguide on CMOS grade silicon with a polyimide interface layer is presented, It is shown that the transmission line can have an attenuation comparable to other transmission lines on Si substrates if the proper polyimide thickness is used.
Power processing electronic systems, data acquiring probes, and signal conditioning circuits are required to operate reliably under harsh environments in many of NASA:s missions. The environment of the space mission as well as the operational requirements of some of the electronic systems, such as infrared-based satellite or telescopic observation stations where cryogenics are involved, dictate the utilization of electronics that can operate efficiently and reliably at low temperatures. In this work, radiation-hard CMOS 8-bit flash A/D converters were characterized in terms of voltage conversion and offset in the temperature range of +25 to -190 C. Static and dynamic supply currents, ladder resistance, and gain and offset errors were also obtained in the temperature range of +125 to -190 C. The effect of thermal cycling on these properties for a total of ten cycles between +80 and - 150 C was also determined. The experimental procedure along with the data obtained are reported and discussed in this paper.
We have developed a hard x-ray coder that provides high angular resolution imaging capability using a coarse position sensitive image plane detector. The coder consists of two Fresnel zone plates. (FZP) Two such 'FZP's generate Moire fringe patterns whose frequency and orientation define the arrival direction of a beam with respect to telescope axis. The image plane detector needs to resolve the Moire fringe pattern. Pixilated detectors can be used as an image plane detector. The recently available 'CMOS' imager could provide a very low power large area image plane detector for hard x-rays. We have looked into a unit made by Rad-Icon Imaging Corp. The Shadow-Box 1024 x-ray camera is a high resolution 1024xl024 pixel detector of 50x50 mm area. It is a very low power, stand alone camera. We present some preliminary results of our investigation of evaluation of such camera.
For the first time, RF MEMS switcbes on CMOS grade Si witb a polyimide interface layer are fabricated and characterized. At Ka-Band (36.6 GHz), an insertion loss of 0.52 dB and an isolation of 20 dB is obtained.
The objective of this work is to design and develop Low-Power RF SOI-CMOS Technology for Distributed Sensor Networks. We briefly report on the accomplishments in this work. We also list the impact of this work on graduate student research training/involvement.
In this letter we present a timing and control strategy that can be used to realize synchronous systems with a level of performance that approaches that of asynchronous circuits or systems. This approach is based upon a single-phase synchronous circuit/system architecture with a variable period clock. The handshaking signals required for asynchronous self-timed circuits are not needed. Dynamic power supply current monitoring is used to generate the timing information, that is comparable to the completion signal found in self-timed circuits; this timing information is used to modi@ the circuit clock period. This letter is concluded with an example of the proposed approach applied to a static CMOS ripple-carry adder.
This viewgraph presentation reviews the tests of a modified commercial CMOS chip for operation in radiation environments. The presentation has pictures of the chip, and charts of the test results.
This paper discusses common approaches to CMOS APS technology, as well as specific results on the five-wire programmable digital camera-on-a-chip developed at JPL. The paper also reports recent research in the design, operation, and performance of APS imagers for several imager applications.
In the present work, the hot-carrier degradation of transistors fabricated by a 0.25- mu m FD SOI CMOS process was investigated.
We report a 64x64 element CMOS active pixel sensor (APS) with ultra-high-dynamic-range linear output. The chip features a new architecture enabling multiple samples per pixel per frame.
A complete programmable digital camera-on-a-chip based on low power active pixel sensor technology is implemented as a single CMOS integrated circuit.
Two charge-scaling successive approximation A/D converters for culumn-parallel data processing in CMOS active pixel image sensors (APS) are presented.
A 128 x 128 element CMOS active pixel image sensor (APS) with on-chip timing, control, and.
A second generation image sensor technology has been developed at the NASA Jet Propulsion Laboratory as a result of the continuing need to miniaturize space science imaging instruments. Implemented using standard CMOS, the active pixel sensor (APS) technology permits the integration of the detector array with on-chip timing, control and signal chain electronics, including analog-to-digital conversion.
A second generation image sensor technology has been developed at the NASA Jet Propulsion Laboratory as a result of the continuing need to miniaturize space science imaging instruments. Implemented using standard CMOS, the active pixel sensor (APS) technology permits the integration of the detector array with on-chip timing, control and signal chain electronics, including analog-to-digital conversion.
An improved state-space analysis of the CMOS static RAM cell is presented. Introducing theconcept of the dividing line, the critical charge for heavy-ion-induced upset of memory cells can becalculated considering symmetrical as well as asymmetrical capacitive loads. From the criticalcharge, the upset-rate per bit-day for static RAMs can be estimated.
The paper introduces an approach to automated synthesis of CMOS circuits, based on evolution on a Programmable Transistor Array (PTA).
A family of CMOS-based active pixel image sensors (APS) that are inherently compatible with the integration of on-chip signal processing circuitry is reported.