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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 1,801 records · Page 100
All sourcesNASA NTRSDOE OSTI
NASA NTRS1975

Space Tug Avionics Definition Study. Volume 5: Cost and Programmatics

The baseline avionics system features a central digital computer that integrates the functions of all the space tug subsystems by means of a redundant digital data bus. The central computer consists of dual central processor units, dual input/output processors, and a fault tolerant memory, utilizing internal redundancy and error checking. Three electronically steerable phased arrays provide downlink transmission from any tug attitude directly to ground or via TDRS. Six laser gyros and six accelerometers in a dodecahedron configuration make up the inertial measurement unit. Both a scanning laser radar and a TV system, employing strobe lamps, are required as acquisition and docking sensors. Primary dc power at a nominal 28 volts is supplied from dual lightweight, thermally integrated fuel cells which operate from propellant grade reactants out of the main tanks.

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NASA NTRS1975

Photographic film image enhancement

A series of experiments were undertaken to assess the feasibility of defogging color film by the techniques of optical spatial filtering. A coherent optical processor was built using red, blue, and green laser light input and specially designed Fourier transformation lenses. An array of spatial filters was fabricated on black and white emulsion slides using the coherent optical processor. The technique was first applied to laboratory white light fogged film, and the results were successful. However, when the same technique was applied to some original Apollo X radiation fogged color negatives, the results showed no similar restoration. Examples of each experiment are presented and possible reasons for the lack of restoration in the Apollo films are discussed.

Horner, J. L.↗
NASA NTRS1974

Mercury bombardment ion thrusters - Development status, performance levels, and test history

The present work describes the development status, performance levels, and life test history of 5-cm, 8-cm, and 30-cm mercury bombardment ion thrusters and their respective power processors. A 2.6 kW, 30-cm thruster module and its power processor unit are now available that established the performance required by interplanetary and geosynchronous orbit raising missions. An 8-cm thruster with nominal 4.5 mN thrust level capability has demonstrated a high performance over a wide range of thrust and operational life.

Molitor, J. H.↗
NASA NTRS1974

Thermal and structural integration problems associated with primary electric propulsion

A typical solar electric propulsion (SEP) spacecraft design which meets challenges posed by the physical characteristics of SEP and by the operational and environmental requirements associated with missions for which SEP is advantageous is used to develop structural and thermal integration requirements which are important to the successful design of electric propulsion elements. Included are discussions on thruster and power processor thermal and structural integration requirements and the definition of representative environmental requirements. Next, an improved power processor packaging concept, referred to as dual shear plate packaging, is described and shown to meet these requirements. Continued development of a two-axis-gimbal thruster array is also described. This concept demonstrates the successful thermal and structural integration of thrusters, propellant feed system, and thrust-vector-control actuators into a modular thrust assembly which meets the needs of a broad range of missions and possible vehicle configurations. Details of this design concept are presented.

Ross, R. G., Jr.↗
NASA NTRS1975

Investigating techniques in the generation of support software

The performance of the Meta assembler processor software package previously provided for the Space Ultrareliable Modular Computer (SUMC) at the Marshall Space Flight Center (MSFC) was verified. A number of adjustments were made to the processor following the rehosting of the SUMC software development facility (S4) on a newly acquired IBM 360/65. The assembler was configured to provide cross assembly capability for various target computers.

Edwards, A. J.↗
NASA NTRS1975

The development of an engineering computer graphics laboratory

Hardware and software systems developed to further research and education in interactive computer graphics were described, as well as several of the ongoing application-oriented projects, educational graphics programs, and graduate research projects. The software system consists of a FORTRAN 4 subroutine package, in conjunction with a PDP 11/40 minicomputer as the primary computation processor and the Imlac PDS-1 as an intelligent display processor. The package comprises a comprehensive set of graphics routines for dynamic, structured two-dimensional display manipulation, and numerous routines to handle a variety of input devices at the Imlac.

Anderson, D. C.↗
NASA NTRS1975

Application of LSI to signal detection: The deltic DFPCC

The development of the DELTIC DFPCC serial mode signal processor is discussed. The processor is designed to detect in the presence of background noise a signal coded into the zero crossings of the waveform. The unique features of the DELTIC DFPCC include versatility in handling a variety of signals and relative simplicity in implementation. A theoretical performance model is presented which predicts the expected value of the output signal as a function of the input signal to noise ratio. Experimental results obtained with the prototype system, which was breadboarded with LSI, MSI and SSI components, are given. The device was compared with other LSI schemes for signal processing and it was concluded that the DELTIC DFPCC is simpler and in some cases more versatile than other systems. With established LSI technology, low frequency systems applicable to sonar and similar problems are feasible.

Gassaway, J. D.↗
NASA NTRS1976

Shared memory for a fault-tolerant computer

A system is described for sharing a memory in a fault-tolerant computer. The memory is under the direct control and monitoring of error detecting and error diagnostic units in the fault-tolerant computer. This computer verifies that data to and from the memory is legally encoded and verifies that words read from the memory at a desired address are, in fact, actually delivered from that desired address. The means are provided for a second processor, which is independent of the direct control and monitoring of the error checking and diagnostic units of the fault-tolerant computer, and to share the memory of the fault-tolerant computer. Circuitry is included to verify that: (1) the processor has properly accessed a desired memory location in the memory; (2) a data word read-out from the memory is properly coded; and (3) no inactive memory was erroneously outputting data onto the shared memory bus.

Gilley, G. C.↗
NASA NTRS1976

SPAR reference manual

The functions and operating rules of the SPAR system, which is a group of computer programs used primarily to perform stress, buckling, and vibrational analyses of linear finite element systems, were given. The following subject areas were discussed: basic information, structure definition, format system matrix processors, utility programs, static solutions, stresses, sparse matrix eigensolver, dynamic response, graphics, and substructure processors.

Whetstone, W. D.↗
NASA NTRS1976

Architecture and data processing alternatives for Tse computer. Volume 1: Tse logic design concepts and the development of image processing machine architectures

Digital computer components which perform two dimensional array logic operations (Tse logic) on binary data arrays are described. The properties of Golay transforms which make them useful in image processing are reviewed, and several architectures for Golay transform processors are presented with emphasis on the skeletonizing algorithm. Conventional logic control units developed for the Golay transform processors are described. One is a unique microprogrammable control unit that uses a microprocessor to control the Tse computer. The remaining control units are based on programmable logic arrays. Performance criteria are established and utilized to compare the various Golay transform machines developed. A critique of Tse logic is presented, and recommendations for additional research are included.

Rickard, D. A.↗
NASA NTRS1976

Software handlers for process interfaces

The principles involved in the development of software handlers for custom interfacing problems are discussed. Handlers for the CAMAC standard are examined in detail. The types of transactions that must be supported have been established by standards groups, eliminating conflicting requirements arising out of different design philosophies and applications. Implementation of the standard handlers has been facilititated by standardization of hardware. The necessary local processors can be placed in the handler when it is written or at run time by means of input/output directives, or they can be built into a high-performance input/output processor. The full benefits of these process interfaces will only be realized when software requirements are incorporated uniformly into the hardware.

Bercaw, R. W.↗
NASA NTRS1976

Demonstration program for Omega receiver prototype microcomputer data processing

The JOLT (TM) commercial microcomputer, based on the MOS Technology 6502 processor chip, for use in Omega navigation system is evaluated. A computer program was prepared in hand-assembled code to demonstrate receiver operation. The processor provides binary processing with interrupts enabled, a carriage return is given to initialize the teleprinter, and a jump is performed to enter the program loop to wait for an interrupt. The program loop operates continuously testing the interrupt flag. The interrupt routine reads the receiver status word and determines whether the current time-slot is the A slot. If so, the interrupt flag, which is also the data index pointer, is reset to zero. The status word is stored in the status buffer. If the time-slot is not A, the interrupt flag/pointer is incremented by one to index the phase and status to the proper buffer words for later use by the print routine.

Lilley, R. W.↗
NASA NTRS1976

Formulation of detailed consumables management models for the development (preoperational) period of advanced space transportation system: Executive summary

Formulation of models required for the mission planning and scheduling function and establishment of the relation of those models to prelaunch, onboard, ground support, and postmission functions for the development phase of space transportation systems (STS) was conducted. The preoperational space shuttle is used as the design baseline for the subject model formulations. Analytical models were developed which consist of a mission planning processor with appropriate consumables data base and a method of recognizing potential constraint violations in both the planning and flight operations functions. A flight data file for storage/retrieval of information over an extended period which interfaces with a flight operations processor for monitoring of the actual flights was examined.

Torian, J. G.↗
NASA NTRS1976

Space shuttle navigation filter development

Problems encountered in developing a high speed trajectory data processor for the shuttle ascent and entry phases are described. The development of a 19 state acceleration filter for the processor is reported.

Lear, W. M.↗
NASA NTRS1976

Onboard Experiment Data Support Facility (OEDSF): Conceptual design study

The Onboard Experimental Data Support Facility (OEDSF) is an inflight data processor based on a totally new architecture specifically developed to cost-effectively process the data of Shuttle payloads sensors. Processing data onboard fills the following needs: (1) reduction of data bulk by conversion to information (2)quick-look for evaluation, interactive operation, etc. (3) real-time computation of engineering representation of sensed phenomena. For example: Value of backscatter coefficient (sigma) of a scatterometer as a function of latitude and longitude (4) exploitation of the real-time availability of ancillary data, thereby obviating the need for time-tagging, recording, and recorrelation and (5) providing data or information immediately usable by the experimenter or user. The OEDSF is made up of modular and cascadable matrix processors. Each matrix has been sized to process the data of a full typical shuttle payload. Cost analyses indicate that significant savings are realized by processing data with the OEDSF compared with conventional ground facilities.

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NASA NTRS1977

Operational compatibility of 30-centimeter-diameter ion thruster with integrally regulated solar array power source

System tests were performed in which Integrally Regulated Solar Arrays (IRSA's) were used to directly power the beam and accelerator loads of a 30-cm-diameter, electron bombardment, mercury ion thruster. The remaining thruster loads were supplied from conventional power-processing circuits. This combination of IRSA's and conventional circuits formed a hybrid power processor. Thruster performance was evaluated at 3/4- and 1-A beam currents with both the IRSA-hybrid and conventional power processors and was found to be identical for both systems. Power processing is significantly more efficient with the hybrid system. System dynamics and IRSA response to thruster arcs are also examined.

Gooder, S. T.↗
NASA NTRS1977

Software design and documentation language

A communications medium to support the design and documentation of complex software applications is studied. The medium also provides the following: (1) a processor which can convert design specifications into an intelligible, informative machine reproducible document; (2) a design and documentation language with forms and syntax that are simple, unrestrictive, and communicative; and (3) methodology for effective use of the language and processor.

Kleine, H.↗
NASA NTRS1977

Feasibility study of microprocessor systems suitable for use in developing a real-time for the 4.75 GHz scatterometer

A class of signal processors suitable for the reduction of radar scatterometer data in real time was developed. The systems were applied to the reduction of single polarized 13.3 GHz scatterometer data and provided a real time output of radar scattering coefficient as a function of incident angle. It was proposed that a system for processing of C band radar data be constructed to support scatterometer system currently under development. The establishment of a feasible design approach to the development of this processor system utilizing microprocessor technology was emphasized.

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