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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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All sourcesNASA NTRSDOE OSTI
DOE OSTI2018

A Fundamental Frequency Sorting Algorithm for Capacitor Voltage Balance of Modular Multilevel Converter With Low-Frequency Carrier Phase Shift Modulation

This paper proposes a fundamental frequency sorting algorithm for balancing the floating capacitors in modular multilevel converters with low-frequency carrier phase shift modulation. The relationship between the driving pulses and submodules (SMs) is rebuilt in every fundamental period by sorting the voltage increments and present voltages. Besides, an improved and simplified strategy is proposed to predict the charging abilities of the driving pulses, so as to avoid sorting the voltage increments. Based on the proposed method, the switching frequency of each power device and the carrier frequency are identical, which reduces the operational losses for applications regarding high power. At the same time, the sorting frequency is as low as the fundamental frequency, which alleviates a large amount of computational cost, and the necessity to measure arm currents is omitted. In this case, the arm current sensors are eliminated, and simplified communication among the central controller and the local ones is set up. Finally, a three-phase 1-MVA simulation platform with 120 SMs and a down-scaled 6-kVA experimental prototype with 48 SMs are constructed to validate the proposed approach.

42 ENGINEERING↗
DOE OSTI2021

A Generic Two-Vector Model Predictive Control for Hybrid Multilevel Converters

In this article, a generic two-vector model predictive control (TV-MPC) strategy is proposed for the hybrid multilevel converters (HMCs). The proposed method selects two optimal voltage vectors among all the vector candidates using a geometric positioning approach to reduce the computational burden, which is a common issue in the existing MPC methods for HMC. Then duty cycles of the two selected vectors are optimized to minimize the current tracking error, such that the current tracking performance can be enhanced compared with the conventional MPC. In addition, the voltages of the floating dc capacitors can be balanced by evaluating all switching sequences that belong to the optimal voltage vectors with optimal duty cycles. Here, the concept of the proposed TV-MPC is generic and applicable for any HMCs. A typical HMC based on active neutral-point-clamped topology is adopted as a case study in this work. Comprehensive simulation and experimental studies are performed on an all silicon-carbide HMC prototype to validate the effectiveness of the proposed control scheme.

42 ENGINEERING↗
DOE OSTI2021

A Phase-Disposition PWM Enabled Model Predictive Control for a Nine-Level Inner-Interleaved Hybrid Multilevel Converter

This article brings forward a phase-disposition pulse width modulation enabled model predictive control (PDPWM-MPC) for a nine-level inner-interleaved hybrid multilevel converter (9L-IHMC). Firstly, three layers of virtual space vector diagrams (VSVD) are established based on the sign patterns of the original and virtual reference vectors in the abcframe, respectively, to achieve the phase-disposition pulse width modulation (PD-PWM) in a non-independent three-phase way. Then, three adjacent virtual vectors in the third-layer VSVD, together with their optimized duty cycles, are applied to guarantee the optimal current tracking. Finally, through the use of the duty cycle alternation approach, dc-link and floating capacitors voltages are balanced and circulating currents are mitigated as well. The proposed PDPWM-MPC can not only enable the decoupling of the low-and high-frequency stages in the 9L-IHMC, but also reduce both output current ripples and computational burden. In addition, it can achieve a constant equivalent switching frequency and address the disproportion of power losses associated with the PD-PWM. Here, both simulations and experiments on a silicon carbide device-based prototype substantiate the effectiveness of the proposed control strategy.

42 ENGINEERING↗
DOE OSTI2017

Fabrication and Modeling of High-Efficiency Front Junction N-Type Silicon Solar Cells With Tunnel Oxide Passivating Back Contact

This paper reports on in-depth understanding, modeling, and fabrication of 23.8% efficient 4 cm 2 n-type Float Zone (FZ) silicon cells with a selective boron emitter and photolithography contact on front and tunnel oxide passivating contact on the back. Tunnel oxide passivating contact composed of a very thin chemically grown silicon oxide (~15 Å) capped with plasma-enhanced chemical vapor deposition (PECVD) grown 20 nm n + poly Si gave excellent surface passivation and carrier selectivity with very low saturation current density (~5 fA/cm 2 ). A high-quality boron selective emitter was formed using ion implantation and solid source diffusion to minimize metal recombination and emitter saturation current density. Process optimization resulted in a cell V oc of 712 mV, J sc of 41.2 mA/cm 2 , and FF of 0.811. Here, a simple methodology is used to model these cells which replaces tunnel oxide passivating contact region by electron and hole recombination velocities extracted from measured saturation current density of tunnel oxide passivating contact region and analysis. Using this approach and two-dimensional device modeling gave an excellent match between the measured and simulated cell parameters and efficiency, supporting excellent passivation and carrier selectivity of these contacts. Extended simulations showed that 26% cell efficiency can be achieved with this cell structure by further optimization of wafer quality, emitter profile, and contact design

14 SOLAR ENERGY↗
DOE OSTI2017

Superacid-Treated Silicon Surfaces: Extending the Limit of Carrier Lifetime for Photovoltaic Applications

Minimizing carrier recombination at interfaces is of extreme importance in the development of high-efficiency photovoltaic devices and for bulk material characterization. Here, we investigate a temporary room temperature superacid-based passivation scheme, which provides surface recombination velocities below 1 cm/s, thus placing our passivation scheme amongst state-of-the-art dielectric films. Application of the technique to high-quality float-zone silicon allows the currently accepted intrinsic carrier lifetime limit to be reached and calls its current parameterization into doubt for 1 Ω·cm n-type wafers. The passivation also enables lifetimes up to 65 ms to be measured in high-resistivity Czochralski silicon, which, to our knowledge, is the highest ever measured in Czochralski-grown material. The passivation strategies developed in this work will help diagnose bulk lifetime degradation under solar cell processing conditions and also help quantify the electronic quality of new passivation schemes.

42 ENGINEERING↗
DOE OSTI2018

DuoModel: Leveraging Reduced Model for Data Reduction and Re-Computation on HPC Storage

High-performance computing (HPC) applications generate large amounts of floating-point data that need to be stored and analyzed efficiently to extract the insights and advance knowledge discovery. With the growing disparities between compute and I/O, optimizing the storage stack alone may not suffice to cure the I/O problem. There has been a strong push in the HPC communities to perform data reduction before data is transmitted to storage in order to lower the I/O cost. However, as of now, neither lossless nor lossy compressors can achieve the adequate reduction ratio that is desired by applications. This paper proposes DuoModel, a new approach that leverages the similarity between the full and reduced application models, and further improve the data reduction ratio. DouModel further improves the compression ratio of state-of-the-art compressors via compressing the differences (termed as delta) between the data products of the two models. For data analytics, the high fidelity data can be re-computed by launching the reduced model and applying the compressed delta. Our evaluations confirm that DuoModel can further push the limit of data reduction while the high fidelity of data is maintained.

Luo, Huizhang (ORCID:0000000323920267)↗
DOE OSTI2023

Statistical Generation of Ocean Forcing With Spatiotemporal Variability for Ice Sheet Models

Melting of ice at the base of floating ice shelves that fringe the Antarctic ice sheet has been identified as a significant source of uncertainty in sea level rise projections. Part of this uncertainty derives from chaotic internal variability of the coupled ocean-atmosphere system. For numerical ice sheet model projections, this uncertainty has not previously been quantified because of the prohibitive computational expense of running large climate model ensembles. Here, we develop and demonstrate a technique that generates independent realizations of internal climate variability from a single climate model simulation. Building on previous developments in model emulation, this technique uses empirical orthogonal function decomposition and Fourier-phase randomization to generate statistically consistent realizations of spatiotemporal variability fields for the target climate variable. The method facilitates efficient sampling of a wide range of climate trajectories, which can also be incorporated within ice sheet or other physical models to represent feedback processes.

54 ENVIRONMENTAL SCIENCES↗
DOE OSTI2022

Bridging Python to Silicon: The SODA Toolchain

Systems performing scientific computing, data analysis, and machine learning tasks have a growing demand for application-specific accelerators that can provide high computational performance while meeting strict size and power requirements. However, the algorithms and applications that need to be accelerated are evolving at a rate that is incompatible with manual design processes based on hardware description languages. Agile hardware design tools based on compiler techniques can help by quickly producing an application-specific integrated circuit (ASIC) accelerator starting from a high-level algorithmic description. Here, we present the software-defined accelerator (SODA) synthesizer, a modular and open-source hardware compiler that provides automated end-to-end synthesis from high-level software frameworks to ASIC implementation, relying on multilevel representations to progressively lower and optimize the input code. Our approach does not require the application developer to write any register-transfer level code, and it is able to reach up to 364 giga floating point operations per second (GFLOPS)/W efficiency (32-bit precision) on typical convolutional neural network operators.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2021

Leveraging In-Network Computing and Programmable Switches for Streaming Analysis of Scientific Data

With the emergence of programmable network devices that match the performance of fixed function devices, several recent projects have explored in-network computing, where the processing that is traditionally done outside the network is offloaded to the network devices. In-network computing has typically been applied to network functions (e.g., load balancing, NAT, and DNS), caching, data reduction/aggregation, and coordination/consensus functions. In some cases it has been used to accelerate stream-processing tasks that involve small payloads and simple operations. In this work we focus on leveraging in-network computing for stream processing of scientific datasets with large payloads that require complex operations such as floating-point computations and logarithmic functions. We demonstrate in-network computing for a real-world scientific application performing streaming normalization of a 2-D image from a light source experiment. We discuss the challenges we encountered and potential approaches to address them.

Sankaran, Ganesh↗
DOE OSTI2018

An Empirical Roofline Methodology for Quantitatively Assessing Performance Portability

System and node architectures continue to diversify to better balance on-node computation, memory capacity, memory bandwidth, interconnect bandwidth, power, and cost for specific computational workloads. For many application developers, achieving performance portability (effectively exploiting the capabilities of multiple architectures) is a desired goal. Unfortunately, dramatically different per-node performance coupled with differences in machine balance can lead to developers being unable to determine whether they have attained performance portability or simply written portable code. The Roofline model provides a means of quantitatively assessing how well a given application makes use of a target platform’s computational capabilities. In this paper, we extend the Roofline model so that it 1) empirically captures a more realistic set of performance bounds for CPUs and GPUs, 2) factors in the true cost of different floating-point instructions when counting FLOPs, 3) incorporates the effects of different memory access patterns, and 4) with appropriate pairing of code performance and Roofline ceiling, facilitates the performance portability analysis.

Computer Science↗
DOE OSTI2021

Adaptive Load Shedding for Grid Emergency Control via Deep Reinforcement Learning

Emergency control, typically such as under-voltage load shedding (UVLS), is broadly used to grapple with low voltage and voltage instability issues in real-world power systems under contingencies. However, existing emergency control schemes are rule-based and cannot be adaptively applied to uncertain and floating operating conditions. Here, we propose an adaptive UVLS algorithm for emergency control via deep reinforcement learning (DRL) and expert systems. We first construct dynamic components for picturing the power system operation as the environment. The transient voltage recovery criteria, which poses time-varying requirements to UVLS, is integrated into the states and reward function to advise the learning of deep neural networks. The proposed method has no tuning issue of coefficients in reward functions, and this issue was regarded as a deficiency in the existing DRL-based algorithms. Case studies illustrate that the proposed method outperforms the traditional UVLS relay in both the timeliness and efficacy for emergency control.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2020

Decay of Electrostatic Force of Dust Particles on Photovoltaic Modules

Photovoltaic (PV) energy yield loss due to solar module soiling has become increasingly important as solar module deployment is now at the hundreds of gigawatts scale and continues to grow rapidly. We have reported on direct measurements-using atomic force microscopy (AFM)-of strong electric-field-induced attraction and adhesion force (Fes) of dust particles onto solar panel that are 1 to 2 orders of magnitude stronger than the van der Waals and water capillary forces, corroborated by observing the increase in system voltage-induced soiling rate. Here, we report another characteristic of Fes on soiling-long lasting or slow decay after turning off the high voltage applied to solar panels. The Fes decay time varies in a wide time range of 1 to 10 hours, depending on two factors: 1) either/both the cell or/and particle were charged with high voltage before the voltages were turned off; and 2) how the cell was connected to the ground after the voltage was turned off-either connected through the power supply electronics, directly connected to the ground, or electrically floated. The Fes decay is understood in terms of 1) net electrical charge dissipations in both particle and cell, 2) thermal disordering of dipole polarization in the module glass dielectrics, and 3) charge redistribution by the electrostatic interaction of particle and module glass. This long-lasting Fes for hours can significantly affect the solar panel soiling after sunset, especially combined with water condensation.

14 SOLAR ENERGY↗
DOE OSTI2020

Scalable Knowledge Graph Analytics at 136 Petaflop/s

We are motivated by newly proposed methods for data mining large-scale corpora of scholarly publications, such as the full biomedical literature, which may consist of tens of millions of papers spanning decades of research. In this setting, analysts seek to discover how concepts relate to one another. They construct graph representations from annotated text databases and then formulate the relationship-mining problem as one of computing all-pairs shortest paths (APSP), which becomes a significant bottleneck. In this context, we present a new high-performance algorithm and implementation of the Floyd-Warshall algorithm for distributed-memory parallel computers accelerated by GPUs, which we call DSNAPSHOT (Distributed Accelerated Semiring All-Pairs Shortest Path). For our largest experiments, we ran DSNAPSHOT on a connected input graph with millions of vertices using 4, 096nodes (24,576GPUs) of the Oak Ridge National Laboratory's Summit supercomputer system. We find DSNAPSHOT achieves a sustained performance of 136×1015 floating-point operations per second (136petaflop/s) at a parallel efficiency of 90% under weak scaling and, in absolute speed, 70% of the best possible performance given our computation (in the single-precision tropical semiring or “min-plus” algebra). Looking forward, we believe this novel capability will enable the mining of scholarly knowledge corpora when embedded and integrated into artificial intelligence-driven natural language processing workflows at scale.

Kannan, Ramakrishnan {ramki}↗
DOE OSTI2024

Breaking the Million-Electron and 1 EFLOP/s Barriers: Biomolecular-Scale Ab Initio Molecular Dynamics Using MP2 Potentials

The accurate simulation of complex biochemical phenomena has historically been hampered by the computational requirements of high-fidelity molecular-modeling techniques. Quantum mechanical methods, such as ab initio wave-function (WF) theory, deliver the desired accuracy, but have impractical scaling for modeling biosystems with thousands of atoms. Combining molecular fragmentation with MP2 perturbation theory, this study presents an innovative approach that enables biomolecular-scale ab initio molecular dynamics (AIMD) simulations at WF theory level. Leveraging the resolution-of-the-identity approximation for Hartree-Fock and MP2 gradients, our approach eliminates computationally intensive four-center integrals and their gradients, while achieving near-peak performance on modern GPU architectures. The introduction of asynchronous time steps minimizes time step latency, overlapping computational phases and effectively mitigating load imbalances. Utilizing up to 9,400 nodes of Frontier and achieving 59% (1006.7 PFLOP/s) of its double-precision floating-point peak, our method enables us to break the million-electron and 1EFLOP/s barriers for AIMD simulations with quantum accuracy.

Kurzak, Jakub↗
DOE OSTI2024

Shifting Between Compute and Memory Bounds: A Compression-Enabled Roofline Model

In the evolving landscape of high-performance computing, especially to fight the end of Moore’s Law and Dennard’s Scaling, the ability to shift between compute-bound and memory-bound states is critical for enhancing adaptability and flexibility to diverse system and domain-specific architectures. Such capability is vital for optimizing performance across distinguished hardware configurations, such as accelerators, memory hierarchies, and cache systems. Despite that ad hoc optimization techniques, such as compressed/approximate computation, have been enabled for compute-/data-intensive computing for improved performance in distinct hardware settings, there lacks an understanding of 1) the rational behind performance improvement; 2) capability of different optimizations; 3) what optimization to respond to specific computational and memory demands. This work proposes a compression-enabled roofline model to facilitate this adaptability with data compression techniques to balance and transform between computational and memory demands. This model enables applications to adjust in response to the specific strengths and limitations of the underlying hardware and system to optimize resource utilization. The effectiveness of this approach is demonstrated with matrix multiplication kernels on different input sizes, with turning on/off various compression techniques, including 1) low-precision floating point; 2) sparse matrix formulation; and 3) compressed arrays with ZFP. By reducing memory transfer volumes and cache misses and increasing data locality and computational intensity through compression, the specific roofline model can transform between compute and memory bounds to align more efficiently with system capabilities. This advancement not only improves overall performance but also maximizes adaptability in diverse computing environments.

Naraparaju, Ramasoumya [University of Washington]↗
DOE OSTI2024

An Efficient Checkpointing System for Large Machine Learning Model Training

As machine learning models increase in size and complexity rapidly, the cost of checkpointing in ML training became a bottleneck in storage and performance (time). For example, the latest GPT-4 model has massive parameters at the scale of 1.76 trillion. It is highly time and storage consuming to frequently writes the model to checkpoints with more than 1 trillion floating point values to storage. This work aims to understand and attempt to mitigate this problem. First, we characterize the checkpointing interface in a collection of representative large machine learning/language models with respect to storage consumption and performance overhead. Second, we propose the two optimizations: i) A periodic cleaning strategy that periodically cleans up outdated checkpoints to reduce the storage burden; ii) A data staging optimization that coordinates checkpoints between local and shared file systems for performance improvement.

machine learning, artificial intelligence↗
DOE OSTI2020

Characterization of Amplification Properties of the Superconducting-Ferromagnetic Transistor

Here we report on the measurement results of the superconducting-ferromagnetic transistors (SFTs). The devices were made at Northwestern University and Hypres (SeeQC), Inc. (Nevirkovets et al., 2014; 2015). SFT is a multiterminal device with the SIS'FIFS (or SFIFS'IS) structure (where S, I, and F denote a superconductor, an insulator, and a ferromagnetic material, respectively) exploiting intense quasiparticle injection in order to modify the nonlinear I-V curve of a superconducting tunnel junction. SFT is capable of providing voltage, current, and power amplification while having good input/output isolation. We characterized the devices using different measurement techniques. We measured S parameters of the single- and double-acceptor devices at frequencies up to 5 MHz. Importantly, we confirmed that the isolation between the input and output of the device is quite good. However, the techniques typically employed to characterize semiconductor devices do not allow for revealing the full potential of our low-resistive SFT devices, especially those having two acceptors. In the latter case, we also tested the devices using the battery-powered current sources with floating grounds. Analyzing double-acceptor I-V curves recorded at different levels of injection currents, for an optimal load, we deduced a small-signal voltage gain of 33 and a power gain of 2.4. We suggest that further improvement of the SFT device parameters is possible in optimized devices, so that the device potentially may serve as a preamplifier for readout of output signals of cryogenic detectors and be useful as an element of other superconductor-based circuits. In addition, we used scanning transmission electron microscopy to identify some problems in the fabrication of the devices without any planarization.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗
DOE OSTI2022

An Accurate, Error-Tolerant, and Energy-Efficient Neural Network Inference Engine Based on SONOS Analog Memory

In this work, we demonstrate SONOS (silicon-oxide-nitrideoxide- silicon) analog memory arrays that are optimized for neural network inference. The devices are fabricated in a 40nm process and operated in the subthreshold regime for in-memory matrix multiplication. Subthreshold operation enables low conductances to be implemented with low error, which matches the typical weight distribution of neural networks, which is heavily skewed toward near-zero values. This leads to high accuracy in the presence of programming errors and process variations. We simulate the end-to-end neural network inference accuracy, accounting for the measured programming error, read noise, and retention loss in a fabricated SONOS array. Evaluated on the ImageNet dataset using ResNet50, the accuracy using a SONOS system is within 2.16% of floating-point accuracy without any retraining. The unique error properties and high On/Off ratio of the SONOS device allow scaling to large arrays without bit slicing, and enable an inference architecture that achieves 20 TOPS/W on ResNet50, a >10× gain in energy efficiency over state-of-the-art digital and analog inference accelerators.

97 MATHEMATICS AND COMPUTING↗

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