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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 181 records · Page 10
All sourcesNASA NTRSDOE OSTI
DOE OSTI2023

Doubling the superconducting transition temperature of ultraclean wafer-scale aluminum nanofilms

Here, we studied the role of reduced dimensionality and disorder in the superconducting properties of wafer-scale aluminum (Al) nanofilms. This new generation of ultrathin films were grown using molecular beam epitaxy and depict normal-state sheet resistance at least 20 times lower than the quantum resistance ℎ⁡/(4⁢𝑒 2 ). Defying general expectations, the superconducting transition temperature of our films increases with decreasing Al film thickness, reaching 2.4 K for a 3.5-nm-thick Al film grown on GaAs: twice that of bulk Al (1.2 K). Surface phonon softening is shown to impact superconductivity in pure ultrathin films, offering a route for materials engineering in two dimensions.

2-dimensional systems↗
DOE OSTI2021

Reactor scale simulations of ALD and ALE: Ideal and non-ideal self-limited processes in a cylindrical and a 300 mm wafer cross-flow reactor

Here, we have developed a simulation tool to model self-limited processes such as atomic layer deposition (ALD) and atomic layer etching inside reactors of arbitrary geometry as well the output of in situ quartz crystal microbalance and mass spectrometry. We have applied this model to two standard types of cross-flow reactors: a cylindrical tube reactor and a model 300 mm wafer reactor, and explored both ideal and nonideal self-limited kinetics. The model results are in agreement with experimental results and analytic expressions obtained using a simple plug-flow model for the cylindrical tube reactor. We also extended the simulations to consider two nonideal self-limited processes: soft-saturating processes characterized by a slow reaction pathway and processes where surface by-products can compete with the precursor for the same pool of adsorption sites. Our results show that it is possible to have a self-limited process with saturated yet inhomogeneous growth profiles due to the competition of reactor by-products. This is in agreement with experimental observations for titanium dioxide ALD from titanium tetraisopropoxide and titanium tetrachloride precursors.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
DOE OSTI2026

Wafer-scale high-k SrTiO 3 dielectrics with rational barrier-layer design for low leakage and high charge density

High-k oxides such as SrTiO 3 promise large capacitance, but their dielectric response is often limited by leakage currents due to reduced bandgaps. We show that introducing a thin barrier layer beneath SrTiO 3 is a simple and effective way to suppress leakage and increase charge density. Using hybrid molecular beam epitaxy, we grew uniform SrTiO 3 films on Nb:SrTiO 3 , CaSnO 3 /Nb:SrTiO 3 , and 2-in. SiO 2 /p-Si stacks to directly compare how different barrier layers influence device behavior. Both CaSnO 3 and SiO 2 reduce leakage, but the ultra-wide-bandgap SiO 2 layer enables much higher operating voltages, yielding charge densities exceeding 5 × 10 13 cm −2 at room temperature—more than a fivefold enhancement compared to devices without a barrier layer. This improvement comes with a predictable trade-off: the lower dielectric constant of SiO 2 reduces overall capacitance, making its thickness an important design parameter. Together, these results demonstrate that rational barrier-layer engineering—including wafer-scale integration on Si—provides a clear pathway to achieving higher charge densities in SrTiO 3 -based dielectric devices.

36 MATERIALS SCIENCE↗
DOE OSTI2023

On-Wafer Wide-Pore Anodic Aluminum Oxide

Anodized aluminum oxide (AAO) has been used as nanotemplates for nanomaterials and nanodevice fabrications. Microfabrication techniques are attracting attention for nanodevice synthesis. However, AAO requires a microfabrication-compatible substrate due to its brittleness. While there are studies that already show AAO on compatible substrates, the pore sizes may not be applicable for multicomponent nanodevices. In this study, wide pore AAOs with ohmic bottom contacts are fabricated on 76 mm Si wafers. Sputtering was used to deposit Al along with supporting layers to achieve this goal. A quiescent electropolishing technique was used to smooth the surface of Al. Standard photolithography was used to define the active area on the Al for anodization. Then 195 V two-step anodization was performed to fabricate wide pore AAOs with pore diameters ranging from 130 ± 32 nm to 400 ± 31 nm with interpore distance of 480 ± 47 nm. Furthermore, it also showed that the ordering of the pores depended on the current density over the more conventional anodization time.

25 ENERGY STORAGE↗
DOE OSTI2022

Ultralow 0.034 dB/m loss wafer-scale integrated photonics realizing 720 million Q and 380 μW threshold Brillouin lasing

We demonstrate 0.034 dB/m loss waveguides in a 200-mm wafer-scale, silicon nitride (Si 3 N 4 ) CMOS-foundry-compatible integration platform. We fabricate resonators that measure up to a 720 million intrinsic Q resonator at 1615 nm wavelength with a 258 kHz intrinsic linewidth. This resonator is used to realize a Brillouin laser with an energy-efficient 380 µW threshold power. The performance is achieved by reducing scattering losses through a combination of single-mode TM waveguide design and an etched blanket-layer low-pressure chemical vapor deposition (LPCVD) 80 nm Si 3 N 4 waveguide core combined with thermal oxide lower and tetraethoxysilane plasma-enhanced chemical vapor deposition (TEOS–PECVD) upper oxide cladding. This level of performance will enable photon preservation and energy-efficient generation of the spectrally pure light needed for photonic integration of a wide range of future precision scientific applications, including quantum, precision metrology, and optical atomic clocks.

Liu, Kaikai (ORCID:0000000213609646)↗
DOE OSTI2021

Wafer-scale remote epitaxy of III-V semiconductors and applications

In conventional epitaxy of single-crystalline semiconductor materials, it is challenging to separate the grown layer with the substrate due to the strong bonding at the interface. Remote epitaxy is a recently discovered method to grow single-crystalline thin films on graphene, wherein the grown film can be exfoliated at the graphene interface to form freestanding membranes. Here, we present our recent development on remote epitaxy of III-V semiconductors. We show that directly growing 2D materials on III-V substrates as a remote epitaxy template is an ideal pathway that can eliminate transfer process-related defects and can realize wafer-scale process of remote epitaxy and substrate reuse. We present the strategies to grow 2D materials on the surface of III-V materials, which is much more challenging than thermally robust substrates such as SiO2/Si or sapphire. The nucleation of III-V on 2D material-coated III-V platforms via remote interaction is investigated both experimentally and theoretically. Lastly, we show advanced remote epitaxial platforms and optoelectronic applications enabled by remote epitaxy, and the capability to recycle the III-V substrates for repeated remote epitaxy and production of freestanding III-V thin films.

Kim, Hyunseok↗
DOE OSTI2021

Wafer-scale remote epitaxy of III-V semiconductors and applications

In conventional epitaxy of single-crystalline semiconductor materials, it is challenging to separate the grown layer with the substrate due to the strong bonding at the interface. Remote epitaxy is a recently discovered method to grow single-crystalline thin films on graphene, wherein the grown film can be exfoliated at the graphene interface to form freestanding membranes. Here, we present our recent development on remote epitaxy of III-V semiconductors. We show that directly growing 2D materials on III-V substrates as a remote epitaxy template is an ideal pathway that can eliminate transfer process-related defects and can realize wafer-scale process of remote epitaxy and substrate reuse. We present the strategies to grow 2D materials on the surface of III-V materials, which is much more challenging than thermally robust substrates such as SiO2/Si or sapphire. The nucleation of III-V on 2D material-coated III-V platforms via remote interaction is investigated both experimentally and theoretically. Lastly, we show advanced remote epitaxial platforms and optoelectronic applications enabled by remote epitaxy, and the capability to recycle the III-V substrates for repeated remote epitaxy and production of freestanding III-V thin films.

Kim, Hyunseok↗
DOE OSTI2024

A Scalable & Non-Destructive Characterization Strategy to Study Semiconductor/Dielectric Interfaces and Predict Wafer-Level Device Performance

The defect density present at the dielectric-semiconductor interface in an MOS structure directly influences the channel carrier characteristics in semiconductor devices, especially in wide bandgap material systems used in power devices. While these trap defects are typically quantified through electrical characterization of MOS-capacitor test structures, this treatment offers very little insight into the physical nature of interface defects. Such shortcomings demand a physical characterization strategy to guide fabrication optimization. X-ray photoelectron spectroscopy (XPS) is suggested as a viable technique to determine chemical data for dielectric interfaces formed using atomic layer deposition (ALD) on GaN substrates. Previously, 1-D XPS characterization has confirmed the presence of a Ga x O y interlayer between ALD dielectrics and the GaN substrate. In this work, XPS data is serially collected to form 2-D images of an ALD-Al 2 O 3 /GaN interface as a proof-of-concept experiment for in-situ XPS quality monitoring during ALD processing. The information provided by this work reveals some of the challenges for incorporating XPS characterization as an in-situ strategy during fabrication of GaN-based devices. Separately, electrical mapping of a 2-D array of ALD-Al 2 O 3 /GaN MOS-capacitor devices provide a means to quantify the spatial variations in interface quality across a single wafer. Physical characterization techniques, such as time-of-flight secondary ion mass spectroscopy, provide additional chemical information about the Al 2 O 3 /Ga x O y /GaN structure that complement the electrical mapping results. This analysis shows that a higher Ga x O y content correlates with higher interface state defects for trap energies deep in the band gap.

42 ENGINEERING↗
DOE OSTI2022

Array of Graphene Variable Capacitors on 100 mm Silicon Wafers for Vibration-Based Applications

Highly flexible, electrically conductive freestanding graphene membranes hold great promise for vibration-based applications. This study focuses on their integration into mainstream semiconductor manufacturing methods. We designed a two-mask lithography process that creates an array of freestanding graphene-based variable capacitors on 100 mm silicon wafers. The first mask forms long trenches terminated by square wells featuring cone-shaped tips at their centers. The second mask fabricates metal traces from each tip to its contact pad along the trench and a second contact pad opposite the square well. A graphene membrane is then suspended over the square well to form a variable capacitor. The same capacitor structures were also built on 5 mm by 5 mm bare dies containing an integrated circuit underneath. We used atomic force microscopy, optical microscopy, and capacitance measurements in time to characterize the samples.

36 MATERIALS SCIENCE↗