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At least 181 records · Page 10

An Set-Free, All Digital Controlled Point-of-Load Regulator for Next Generation Power Systems: ADC-POL

This paper presents a digitally controlled programmable point-of-load regulator for next-generation power systems. A novel digital control scheme was designed to minimize single-event effect (SEE)-induced transient effects. By effectively programming the loop transmission, the POL can trade off transient response time with SET robustness. The IC works with 1 to 5.5 V input voltage, 1-4.5V regulated output voltage, high efficiency (peak efficiency at 94%) and power of up to 5 W. The design was fabricated in the AMI i2t100 0.7 mu m complimentary, metal-oxide semiconductor (CMOS) process and characterized with the Jet Propulsion Laboratory (JPL) pulsed laser system.

Digital Signal Processing (DP)

Radiation effects assessment of MRAM devices

The Magneto-resistive Random Access Memory (MRAM) from Freescale Semiconductor, MR2A16A, was subjected to heavy ion single event testing. Test results show that this device is sensitive to Single Event Latchup (SEL). The sensitivity of the MRAM was attributed to the complementary metal oxide semiconductor (CMOS) process in which the active portion of this device is constructed. Therefore, the device must be used with caution and may require mitigation techniques if used in a space environment. There was no indication that the MRAM technology itself, the memory element construction, is subject to damage from heavy ions.

McClure, Steve

Real time quantitative imaging for semiconductor crystal growth, control and characterization

A quantitative real time image processing system has been developed which can be software-reconfigured for semiconductor processing and characterization tasks. In thermal imager mode, 2D temperature distributions of semiconductor melt surfaces (900-1600 C) can be obtained with temperature and spatial resolutions better than 0.5 C and 0.5 mm, respectively, as demonstrated by analysis of melt surface thermal distributions. Temporal and spatial image processing techniques and multitasking computational capabilities convert such thermal imaging into a multimode sensor for crystal growth control. A second configuration of the image processing engine in conjunction with bright and dark field transmission optics is used to nonintrusively determine the microdistribution of free charge carriers and submicron sized crystalline defects in semiconductors. The IR absorption characteristics of wafers are determined with 10-micron spatial resolution and, after calibration, are converted into charge carrier density.

Wargo, Michael J.

Semiconductor photoelectrochemistry

Semiconductor photoelectrochemical reactions are investigated. A model of the charge transport processes in the semiconductor, based on semiconductor device theory, is presented. It incorporates the nonlinear processes characterizing the diffusion and reaction of charge carriers in the semiconductor. The model is used to study conditions limiting useful energy conversion, specifically the saturation of current flow due to high light intensity. Numerical results describing charge distributions in the semiconductor and its effects on the electrolyte are obtained. Experimental results include: an estimate rate at which a semiconductor photoelectrode is capable of converting electromagnetic energy into chemical energy; the effect of cell temperature on the efficiency; a method for determining the point of zero zeta potential for macroscopic semiconductor samples; a technique using platinized titanium dioxide powders and ultraviolet radiation to produce chlorine, bromine, and iodine from solutions containing their respective ions; the photoelectrochemical properties of a class of layered compounds called transition metal thiophosphates; and a technique used to produce high conversion efficiency from laser radiation to chemical energy.

Buoncristiani, A. M.

Photorefractive Semiconductors and Applications

Photorefractive semiconductors are attractive for information processing, becuase of fast material response, compatibility with semiconductor lasers, and availability of cross polarization diffraction for enhancing signal-to-noise ration. This paper presents recent experimental results on information processing using photorefractive GaAs, InP and CdTe, including image processing with semiconductor lasers.

Photorefractive Semiconductors

A U.S. view of silicon production processes

One of the objectives of the Low-Cost Solar Array Project is the demonstration of the practicality of processes for producing silicon, suitable for fabricating solar cells for terrestrial applications, at prices less than $14/kg. Approaches being investigated are related to a metallurgical silicon/silane/silicon process, a metallurgical silicon/dichlorosilane/Siemens-type process, and a silicon tetrachloride-zinc reduction process. There is a great probability that the first process will yield semiconductor grade Si at a price less than $14/kg. The second process appears to be capable of providing polysilicon with a purity equivalent to the present commercial semiconductor grade silicon at a price of about $20/kg. An important part of the program is the investigation of the effects of impurities on the performance of solar cells.

Lutwack, R.

Forming electrical interconnections through semiconductor wafers

An information processing system based on CMOS/SOS technology is being developed by NASA to process digital image data collected by satellites. An array of holes is laser drilled in a semiconductor wafer, and a conductor is formed in the holes to fabricate electrical interconnections through the wafers. Six techniques are used to form conductors in the silicon-on-sapphire (SOS) wafers, including capillary wetting, wedge extrusion, wire intersection, electroless plating, electroforming, double-sided sputtering and through-hole electroplating. The respective strengths and weaknesses of these techniques are discussed and compared, with double-sided sputtering and the through-hole plating method achieving best results. In addition, hollow conductors provided by the technique are available for solder refill, providing a natural way of forming an electrically connected stack of SOS wafers.

Anthony, T. R.

Importance of finite-size corrections for accurate ab initio modeling of carrier capture at semiconductor defects: A case study of substitutional C N in GaN

In ab initio studies of carrier-capture processes in defective semiconductor materials, the single-effective-mode formalism and the static-coupling approximation have become the predominant theoretical approaches for determining carrier-capture coefficients. The single-mode formalism relies on accurate nonequilibrium defect energies obtained from density-functional theory (DFT), where required inputs are a series of configurationally displaced, defect-containing supercells obtained using an interpolative ansatz, and where the DFT outputs are corresponding total energies that have traditionally been postprocessed using a long-established ground-state formulation of finite-size corrections and defect-formation energies. This formulation remains commonly used even though the defects that form a configuration-coordinate (CC) diagram typically exist as structures that are displaced from the ground state. To remedy this inconsistency, Kumagai has recently proposed novel methods for implementing finite-size corrections specifically intended for DFT calculations of the defect energies used to construct CC diagrams and implement the single-mode formalism [Y. Kumagai, Phys. Rev. B 107, L220101 (2023)]. Kumagai's approach builds on the latest finite-size-correction methods introduced to describe vertical charge-state transitions for charge-localizing point defects in semiconductors and insulators [T. Gake et al., Phys. Rev. B 101, 020102 (2020); S. Falletta et al., Phys. Rev. B 102, 041115 (2020)]. The newly identified finite-size artifact treated in these studies is the polarization charge induced on a configurationally frozen defect and its subsequent interaction with a vertical transition in charge state. In this work, we evaluate Kumagai's proposed methodology by applying it in a high-precision DFT study of carrier capture by substitutional C N in GaN, a well-characterized and technologically relevant defect and material. We have rigorously calculated C N defect energies across various supercell sizes for each defect configuration and charge state on the hole-capture CC diagram of C N (𝑞=−1), enabling a direct comparison of the slopes of the defect energies versus inverse cell size with those predicted by Kumagai. The most consequential prediction of Kumagai's method is that these slopes distinctly vary as the square of the linear-interpolation parameter used to construct the nonequilibrium defect configurations. Our results quantitatively support this prediction. Moreover, with these new finite-size corrections and multiple-cell-size DFT calculations in place, we find that the classical energy barrier for hole capture by C N (𝑞=−1) in GaN decreases to 0.092–0.127 eV. This finding confirms the recent ≈ 0.1 eV prediction of Reshchikov based on the weak temperature dependence for hole capture observed in photoluminescence experiments [M. A. Reshchikov, J. Appl. Phys. 129, 121101 (2021)]. These results stand in stark contrast to previously calculated barriers of 0.486 and 0.73 eV, which also used the single-mode formalism but were obtained by instead using ground-state-based finite-size corrections. Our reduced classical barrier for capture increases the temperature-dependent hole-capture coefficient of a C N (𝑞=−1) defect by more than two to four orders of magnitude for temperatures of 100–600 K, compared to the previous 0.486 eV results. While other defects may not be as dramatically affected as here, we suggest that incorporating proper finite-size corrections for the vertical-transition-like states embedded within CC diagrams is an essential, yet previously unrecognized, component of accurate modeling of carrier-capture when using the single-effective-mode formalism.

dielectric properties

Economics of polysilicon processes

Techniques are being developed to provide lower cost polysilicon material for solar cells. Existing technology which normally provides semiconductor industry polysilicon material is undergoing changes and also being used to provide polysilicon material for solar cells. Economics of new and existing technologies are presented for producing polysilicon. The economics are primarily based on the preliminary process design of a plant producing 1,000 metric tons/year of silicon. The polysilicon processes include: Siemen's process (hydrogen reduction of trichlorosilane); Union Carbide process (silane decomposition); and Hemlock Semiconductor process (hydrogen reduction of dichlorosilane). The economics include cost estimates of capital investment and product cost to produce polysilicon via the technology. Sensitivity analysis results are also presented to disclose the effect of major paramentes such as utilities, labor, raw materials and capital investment.

Yaws, C. L.

Eliminating Signal Bias Caused by Vacuum System Backstreaming in the Diagnostic Residual Gas Analyzer of ITER

In fusion neutral gas analysis, such as with the Diagnostic Residual Gas Analyzer (DRGA) for ITER, the primary measurement range of interest comprises the low-amu species (1 to 6), especially deuterium and helium. The challenge in successfully obtaining accurate measurements is two-fold. First, the sensitivity of the method must be sufficient to resolve trace amounts accurately; typically, one percent or less. Second, the gas signal from the fusion processes must be free of bias caused by the latent presence (from system outgassing and/or vacuum backstreaming) of these gases to enable accurate interpretation of the measured signal. This latter criterion can be problematic for the lightest gases since there is a propensity for some fraction of the pumped gas load to undergo a phenomenon known as backstreaming. This behavior is manifested in pumping systems for gas properties related to relative atomic weight (lightest) and size (smallest). Backstreaming results in a significant amount of the pumped gas undertaking a reverse flow and re-entering the measurement region; thus, contaminating the forward, real-time measurement. To fully eliminate this adverse effect, a conductance-limiting device – or orifice – has been installed in the high-vacuum pumping system of the present ITER DRGA prototype. The system was already equipped with a secondary turbomolecular pump (TMP), but with limited effectiveness against backstreaming in the inter-pump volume (IPV). This orifice is placed within the suction inlet coupling of the secondary TMP, which is downstream of the IPV. Its objective is to eliminate the backstreaming phenomenon by increasing the back pressure in the IPV. However, the orifice sizing must take into consideration other factors, such as the diagnostic measurement objectives. For example, in the ITER DRGA, one of the measurement requirements is a dynamic response time of ~1s. Fortunately, an added benefit of the pumping restriction created by the orifice is that the upstream pressure increase is beneficial for the DRGA’s optical gas analysis (OGA) sensors. These sensors are attached to the IPV in the present design. The glow discharges, when used as an OGA light source, will typically have a brighter light emission with increasing plasma cell pressure. In addition to the fusion machine research sector, there are other potential applications of this pumping technique where the monitoring of lighter gas concentrations is essential, such as the photolithography process for the semiconductor fabrication of integrated circuits. This presentation will describe the vacuum system used to demonstrate a process to eliminate backstreaming as well as show test results to verify the accomplishment of this critical objective.

Marcus, Chris

Thermal Diffusivity for III-VI Semiconductor Melts at Different Temperatures

The change of the thermal properties of semiconductor melts reflects the structural changes inside the melts, and a fundamental understanding of this structural transformation is essential for high quality semiconductor crystal growth process. This paper focused on the technical development and the measurement of thermal properties of III-VI semiconductor melts at high temperatures. Our previous work has improved the laser flash method for the specialized quartz sample cell. In this paper, we reported the results of our recent progress in further improvements of the measurement system by minimizing the free convection of the melt, adding a front IR detector, and placing the sample cell in a vacuum environment. The results for tellurium and selenium based compounds, some of which have never been reported in the literature, were obtained at different temperatures as a function of time. The data were compared with other measured thermophysical properties to shed light on the structural transformations of the melt.

Ban, H.

Radiation-Hard SpaceWire/Gigabit Ethernet-Compatible Transponder

A radiation-hard transponder was developed utilizing submicron/nanotechnology from IBM. The device consumes low power and has a low fabrication cost. This device utilizes a Plug-and-Play concept, and can be integrated into intra-satellite networks, supporting SpaceWire and Gigabit Ethernet I/O. A space-qualified, 100-pin package also was developed, allowing space-qualified (class K) transponders to be delivered within a six-month time frame. The novel, optical, radiation-tolerant transponder was implemented as a standalone board, containing the transponder ASIC (application specific integrated circuit) and optical module, with an FPGA (field-programmable gate array) friendly parallel interface. It features improved radiation tolerance; high-data-rate, low-power consumption; and advanced functionality. The transponder utilizes a patented current mode logic library of radiation-hardened-by-architecture cells. The transponder was developed, fabricated, and radhard tested up to 1 MRad. It was fabricated using 90-nm CMOS (complementary metal oxide semiconductor) 9 SF process from IBM, and incorporates full BIT circuitry, allowing a loop back test. The low-speed parallel LVCMOS (lowvoltage complementary metal oxide semiconductor) bus is compatible with Actel FPGA. The output LVDS (low-voltage differential signaling) interface operates up to 1.5 Gb/s. Built-in CDR (clock-data recovery) circuitry provides robust synchronization and incorporates two alarm signals such as synch loss and signal loss. The ultra-linear peak detector scheme allows on-line control of the amplitude of the input signal. Power consumption is less than 300 mW. The developed transponder with a 1.25 Gb/s serial data rate incorporates a 10-to-1 serializer with an internal clock multiplication unit and a 10-1 deserializer with internal clock and data recovery block, which can operate with 8B10B encoded signals. Three loop-back test modes are provided to facilitate the built-in-test functionality. The design is based on a proprietary library of differential current switching logic cells implemented in the standard 90-nm CMOS 9SF technology from IBM. The proprietary low-power LVDS physical interface is fully compatible with the SpaceWire standard, and can be directly connected to the SFP MSA (small form factor pluggable Multiple Source Agreement) optical transponder. The low-speed parallel interfaces are fully compatible with the standard 1.8 V CMOS input/output devices. The utilized proprietary annular CMOS layout structures provide TID tolerance above 1.2 MRad. The complete chip consumes less than 150 mW of power from a single 1.8-V positive supply source.

Katzman, Vladimir

A review of the silicon material task

The Silicon Material Task of the Flat-Plate Solar Array Project was assigned the objective of developing the technology for low-cost processes for producing polysilicon suitable for terrestrial solar-cell applications. The Task program comprised sections for process developments for semiconductor-grade and solar-cell-grade products. To provide information for deciding upon process designs, extensive investigations of the effects of impurities on material properties and the performance of cells were conducted. The silane process of the Union Carbide Corporation was carried through several stages of technical and engineering development; a pilot plant was the culmination of this effort. The work to establish silane fluidized-bed technology for a low-cost process is continuing. The advantages of the use of dichlorosilane is a siemens-type were shown by Hemlock Semiconductor Corporation. The development of other processes is described.

Lutwack, R.