Investigation of new concepts of adaptive devices Quarterly technical report, 3 Dec. 1968 - 2 Mar. 1969
Conduction mechanisms and transient behavior of memory device using semiconductor devices
Lewis, E.↗
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Results for “semiconductor devices”
Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.
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Surface modification using low energy ground state ion beams
A method of effecting modifications at the surfaces of materials using low energy ion beams of known quantum state, purity, flux, and energy is presented. The ion beam is obtained by bombarding ion-generating molecules with electrons which are also at low energy. The electrons used to bombard the ion generating molecules are separated from the ions thus obtained and the ion beam is directed at the material surface to be modified. Depending on the type of ion generating molecules used, different ions can be obtained for different types of surface modifications such as oxidation and diamond film formation. One area of application is in the manufacture of semiconductor devices from semiconductor wafers.
Chutjian, Ara↗
Packaging Technology Developed for High-Temperature SiC Sensors and Electronics
A ceramic- and thick-film-materials-based prototype electronic package designed for silicon carbide (SiC) high-temperature sensors and electronics has been successfully tested at 500 C in an oxygen-containing air environment for 500 hours. This package was designed, fabricated, assembled, and electronically evaluated at the NASA Glenn Research Center at Lewis Field with an in-house-fabricated SiC semiconductor test chip. High-temperature electronics and sensors are necessary for harsh-environment space and aeronautical applications, such as space missions to the inner solar system or the emission control electronics and sensors in aeronautical engines. Single-crystal SiC has such excellent physical and chemical material properties that SiC-based semiconductor electronics can operate at temperatures over 600 C, which is significantly higher than the limit for Si-based semiconductor devices. SiC semiconductor chips were recently demonstrated to be operable at temperatures as high as 600 C, but only in the probe station environment because suitable packaging technology for sensors and electronics at temperatures of 500 C and beyond did not exist. Thus, packaging technology for SiC-based sensors and electronics is immediately needed for both application and commercialization of high-temperature SiC sensors and electronics. In response to this need, researchers at Glenn designed, fabricated, and assembled a prototype electronic package for high-temperature electronics, sensors, and microelectromechanical systems (MEMS) using aluminum nitride (AlN) substrate and gold (Au) thick-film materials. This prototype package successfully survived a soak test at 500 C in air for 500 hours. Packaging components tested included thick-film high-temperature metallization, internal wire bonds, external lead bonds, and a SiC diode chip die-attachment. Each test loop, which was composed of thick-film printed wire, wire bond, and lead bond was subjected to a 50-mA direct current for 250 hours at 500 C.
Chen, Liang-Yu↗
Science challenges and research opportunities for plasma applications in microelectronics
Low-temperature plasmas (LTPs) are essential to manufacturing devices in the semiconductor industry, from creating extreme ultraviolet photons used in the most advanced lithography to thin film etching, deposition, and surface modifications. It is estimated that 40%–45% of all process steps needed to manufacture semiconductor devices use LTPs in one form or another. LTPs have been an enabling technology in the multidecade progression of the shrinking of device dimensions, often referred to as Moore’s law. New challenges in circuit and device design, novel materials, and increasing demands to achieve environmentally benign processing technologies require advances in plasma technology beyond the current state-of-the-art. The Department of Energy Office of Science Fusion Energy Sciences held a workshop titled Plasma Science for Microelectronics Nanofabrication in August 2022 to discuss the plasma science challenges and technical barriers that need to be overcome to continue to develop the innovative plasma technologies required to support and advance the semiconductor industry. One of the key outcomes of the workshop was identifying a set of priority research opportunities (PROs) to focus attention on the most strategic plasma science challenges to address to benefit the semiconductor industry. For each PRO, scientific challenges and recommended strategies to address those challenges were identified. Furthermore, this article summarizes the PROs identified by the workshop participants.
36 MATERIALS SCIENCE↗
Analysis of Carbon Nanotube Metal-Semiconductor Diode Device
We study recently reported drain current Id-drain voltage Vd characteristics of a carbon nanotube metal semiconductor diode device with the gate voltage Vg applied to modulate the carrier density in the nanotube. The diode was kink-shaped at the metal-semiconductor interface. It was shown that (1) larger negative Vg blocked Id more effectively in the negative Vd region, resulting in the rectifying Id-Vd characteristics, and that (2) positive Vg allowed Id in the both Vd polarities, resulting in the non-rectifying characteristics. The negative Vd was the Schottky reverse direction, judging from the negligible Id behavior for a wide region of -4 V less than Vd less than 0 V, with Vg = -4 V. Such negative Vg would attract positive charges from the metallic electrodes (charge reservoir) to the nanotube and lower the nanotube Fermi energy (EF). With larger negative Vg, the experiment showed that the Schottky forward direction (Vd greater than 0) had a smaller turn-on voltage and the Schottky reverse direction (Vd less than 0) was more resistant to the tunneling breakdown. Therefore, the majority carriers in the transport would be electrons since they can see a lower tunneling barrier (shallower built-in potential) in the forward direction when EF is lowered, and a thicker tunneling barrier (Schottky barrier) in the reverse direction due to the reduction in the electron density when EF is lowered.
Yamada, Toshishige↗
Radiation Resistant Silicon Semiconductor Devices-Patent
Improving radiation resistance of silicon semiconductor junctions by doping with lithium
Wysocki, J. J.↗
Analysis of Carbon Nanotube Metal-Semiconductor Diode Device
We study recently reported drain current I(sub d)-drain voltage V(sub d) characteristics of a carbon nanotube metal-semiconductor diode device with the gate voltage V(sub g) applied to modulate the carrier density in the nanotube. The diode was kink-shaped at the metal-semiconductor interface. It was shown that (1) larger negative V(sub g) blocked I(sub d) more effectively in the negative V(sub d) region, resulting in the rectifying I(sub d)-V(sub d) characteristics, and that (2) positive V(sub g) allowed I(sub d) in the both V(sub d) polarities, resulting in the non-rectifying characteristics. The negative V(sub d) was the Schottky reverse direction, judging from the negligible I(sub d) behavior for a wide region of -4 V (is less than) V(sub d) (is less than) 0 V, with V(sub g) = -4 V. Such negative V(sub g) would attract positive charges from the metallic electrodes (charge reservoir) to the nanotube and lower the nanotube Fermi energy (E(sub F)). With larger negative V(sub g), the experiment showed that the Schottky forward direction (V(sub d) (is greater than) 0) had a smaller turn-on voltage and the Schottky reverse direction (V(sub d) (is less than) 0) was more resistant to the tunneling breakdown. Therefore, the majority carriers in the transport would be electrons since they can see a lower tunneling barrier (shallower built-in potential) in the forward direction when E(sub F) is lowered, and a thicker tunneling barrier (Schottky barrier) in the reverse direction due to the reduction in the electron density when E(sub F) is lowered.
Yamada, Toshishige↗
Integrated circuits with programmable gate timing signal generation for power converters and apparatus comprising the same
An apparatus is disclosed that includes a semiconductor device to control a power converter having two or more power FETs. The semiconductor device includes a gate signal generator configured to produce two or more gate signals able to drive the two or more FETs. The gate signal generator has programmable timing configuration parameters to control operation of the two or more gate signals, wherein the timing configuration parameters are digitally programmed via a memory in the semiconductor device. The memory may be implemented with fuses, other non-volatile memory or volatile memory. The parameters may be fixed or updated during a lifetime of the apparatus. A serial-to-parallel conversion may be used to input the parameters. Optimization methods may be performed to determine parameters considered to be optimal. The apparatus may also include the power converter.
42 ENGINEERING↗
Polycrystalline or amorphous semiconductor photovoltaic device having improved collection efficiency
A body of semiconductor material having a first surface and a second surface spaced from the first surface includes a first layer along the first surface, a second layer along the second surface, a third layer between and contiguous to the first and second layers. The third layer is of a conductivity type opposite that of the first and second layers so as to form first and second P-N junctions respectively therebetween. The thickness of the third layer is at least twice the minority carrier diffusion length of the semiconductor material, so that carriers generated within the third layer have a high probability of being collected by one of the P-N junctions. The body includes means for electrically connecting the first and second P-N junctions and means for transferring the carriers collected at the first P-N junction to a portion of the first surface.
Kressel, Henry↗
Optical coupler for heterogeneous integration
In an optical apparatus, an introduced semiconductor device is heterointegrated on a silicon-based platform containing a silicon-based waveguide. A polymeric waveguide is optically coupled to the introduced semiconductor device and overlies at least a portion of the silicon-based waveguide. The polymeric waveguide is conformed as a multimode interference (MMI) coupler between the introduced semiconductor device and the silicon-based waveguide. At least the polymeric waveguide, and in embodiments, also the silicon-based waveguide, is tapered with a shape that effectuates optical coupling to the silicon-based waveguide.
Gehl, Michael↗
A perspective on the electro-thermal co-design of ultra-wide bandgap lateral devices
Fundamental research and development of ultra-wide bandgap (UWBG) semiconductor devices are under way to realize next-generation power conversion and wireless communication systems. Devices based on aluminum gallium nitride (AlxGa1-xN, x is the Al composition), ..beta..-phase gallium oxide (..beta..-Ga2O3), and diamond give promise to the development of power switching devices and radio frequency power amplifiers with higher performance and efficiency than commercial wide bandgap semiconductor devices based on gallium nitride (GaN) and silicon carbide (SiC). However, one of the most critical challenges for the successful deployment of UWBG device technologies is to overcome adverse thermal effects that impact the device performance and reliability. Overheating of UWBG devices originates from the projected high power density operation and poor intrinsic thermal properties of AlxGa1-xN and ..beta..-Ga2O3. This Perspective delineates the need and process for the "electro-thermal co-design" of laterally configured UWBG electronic devices and provides a comprehensive review of current state-of-the-art thermal characterization methods, device thermal modeling practices, and both device- and package-level thermal management solutions.
71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
Overcash, D. R.
The objectives of this investigation were to determine the characteristics of semiconductor devices at low temperatures. The output characteristics of several currently available semiconductor devices and devices fabricated at Marshall Space Flight Center were measured over a range of gate voltages. Large variations in low-temperature performance, not only from type to type, but from field effect transistor (FET) to FET of the same type were obtained. By increasing the carrier concentrations at low temperatures through extra heavy doping, metal oxide semiconductor field effect transistor (MOSFET) device was fabricated that operated at 4.2K. To verify the low-temperature operation of a heavily doped device, this procedure was repeated. Their noise spectrum was analyzed at 4.2K. Suggestions were made as to possible fabrication methods, techniques, and other semiconductor materials that might improve the device charactersitics at low temperatures. A procedure for using an electric field to drift dopants through the insulating oxide to produce a very thin, heavily doped region under the gate of a MOSFET was initiated. Capacitance s a function of voltage plots was suggested as a method for determining the level of dopant drift.
Source record↗
Metallurgical aspects in failed electrical and electronic devices
Electrical and electronic semiconductor device failures from metallurgical viewpoint
Babecki, A. J.↗
Gallium Oxide Heterojunction Diodes for 400 °C High‐Temperature Applications
β ‐Ga 2 O 3 ‐based semiconductor devices are expected to have significantly improved high‐power and high‐temperature performance due to its ultrawide bandgap of close to 5 eV. However, the high‐temperature operation of these ultrawide‐bandgap devices is usually limited by the relatively low 1–2 eV built‐in potential at the Schottky barrier with most high‐work‐function metals. Herein, heterojunction p ‐NiO/n‐ β ‐Ga 2 O 3 diodes fabrication and optimization for high‐temperature device applications are reported, demonstrating a current rectification ratio ( I ON / I OFF ) of more than 10 6 at 410 °C. The NiO heterojunction diode can achieve higher turn‐on ( V ON ) voltage and lower reverse leakage current compared to the Ni‐based Schottky diode fabricated on the same single‐crystal β ‐Ga 2 O 3 substrate, despite charge transport dominated by interfacial recombination. Electrical characterization and device modeling show that these advantages are due to a higher built‐in potential and additional band offset. These results suggest that heterojunction p–n diodes based on β ‐Ga 2 O 3 can significantly improve high‐temperature electronic device and sensor performance.
Sohel, Shahadat H.↗
JANTX1N5623 switching diode
Report describes effects of power and temperature overstress on Semtech and Micro Semiconductor devices. Only two Semtech diodes failed catastrophically. Testing on Micro Semiconductor devices stopped because failure limit was reached. Micro diodes suffered lead separation.
Source record↗
Artifacts for Calibration of Submicron Width Measurements
Artifacts that are fabricated with the help of molecular-beam epitaxy (MBE) are undergoing development for use as dimensional calibration standards with submicron widths. Such standards are needed for calibrating instruments (principally, scanning electron microscopes and scanning probe microscopes) for measuring the widths of features in advanced integrated circuits. Dimensional calibration standards fabricated by an older process that involves lithography and etching of trenches in (110) surfaces of single-crystal silicon are generally reproducible to within dimensional tolerances of about 15 nm. It is anticipated that when the artifacts of the present type are fully developed, their critical dimensions will be reproducible to within 1 nm. These artifacts are expected to find increasing use in the semiconductor-device and integrated- circuit industries as the width tolerances on semiconductor devices shrink to a few nanometers during the next few years. Unlike in the older process, one does not rely on lithography and etching to define the critical dimensions. Instead, one relies on the inherent smoothness and flatness of MBE layers deposited under controlled conditions and defines the critical dimensions as the thicknesses of such layers. An artifact of the present type is fabricated in two stages (see figure): In the first stage, a multilayer epitaxial wafer is grown on a very flat substrate. In the second stage, the wafer is cleaved to expose the layers, then the exposed layers are differentially etched (taking advantage of large differences between the etch rates of the different epitaxial layer materials). The resulting structure includes narrow and well-defined trenches and a shelf with thicknesses determined by the thicknesses of the epitaxial layers from which they were etched. Eventually, it should be possible to add a third fabrication stage in which durable, electronically inert artifacts could be replicated in diamondlike carbon from a master made by MBE and etching as described above.
Grunthaner, Frank↗
Thermal Management for Planar Package Power Electronics (CRADA Final Report)
The National Renewable Energy Laboratory (NREL) and John Deere Electronic Solutions (JDES) collaborated to develop and evaluate computer models and simulations related to the thermal performance of semiconductor device packaging for an inverter of an off-road vehicle ("Semiconductor Packaging"). The objective of the research was for NREL and JDES to develop a two or three-dimensional computer-aided design model of the Semiconductor Packaging ("Computer Model") for thermal performance evaluation in a simulation. The project developed computer models of a Semiconductor Package of silicon-carbide semiconductor devices with appropriate thermal dissipation via one or more of the following thermal features: a double-sided planar cooling configuration, an air-cooled configuration, a liquid-cooled configuration for off-road inverter applications in a relevant simulated operating environment. It is noted that surface area and prototype product embodiment consisting of air-cooled and liquid-cooled configurations may and may not be in direct contact with power semiconductor chips. The idea was to explore and develop packaging and thermal management technology for power semiconductors that was most effective in the performance yet had least burden in overall product cost for a given application.
33 ADVANCED PROPULSION SYSTEMS↗
Performance issues for iterative solvers in device simulation
Due to memory limitations, iterative methods have become the method of choice for large scale semiconductor device simulation. However, it is well known that these methods still suffer from reliability problems. The linear systems which appear in numerical simulation of semiconductor devices are notoriously ill-conditioned. In order to produce robust algorithms for practical problems, careful attention must be given to many implementation issues. This paper concentrates on strategies for developing robust preconditioners. In addition, effective data structures and convergence check issues are also discussed. These algorithms are compared with a standard direct sparse matrix solver on a variety of problems.
Fan, Qing↗