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All sourcesNASA NTRSDOE OSTI
NASA NTRS2018

NASA Electronic Parts and Packaging (NEPP) Field Programmable Gate Array (FPGA) Single Event Effects (SEE) Test Guideline Update

The following are updated or new subjects added to the FPGA SEE Test Guidelines manual: academic versus mission specific device evaluation, single event latch-up (SEL) test and analysis, SEE response visibility enhancement during radiation testing, mitigation evaluation (embedded and user-implemented), unreliable design and its affects to SEE Data, testing flushable architectures versus non-flushable architectures, intellectual property core (IP Core) test and evaluation (addresses embedded and user-inserted), heavy-ion energy and linear energy transfer (LET) selection, proton versus heavy-ion testing, fault injection, mean fluence to failure analysis, and mission specific system-level single event upset (SEU) response prediction. Most sections within the guidelines manual provide information regarding best practices for test structure and test system development. The scope of this manual addresses academic versus mission specific device evaluation and visibility enhancement in IP Core testing.

Test guidelines↗
NASA NTRS1989

Geometric transformations for video compression and human teleoperator display

A method for bandwidth-efficient processing of video imagery to be viewed by the teleoperator of a remotely-operated vehicle on which the camera is mounted is described. The method comprises image coding, transmission, and reconstruction. It is assumed that the transmission bandpass is the limiting factor rather than encoding/decoding schemata; that image coding and reconstruction will be done within the general abilities of the NASA/TI Programmable Remapper; and that the ratio of retained local detail to the operator's visual resolution is held constant throughout the large-field image that is seen. Novel features include that the compression and reconstruction address certain characteristics of the human visual system, that two-way communication controls a moving 'fovea' in the transformation, and that resolution varies over the image. Conventional motivations accommodated include the Cartesian raster-scan nature of available imagers and display devices and a need for low bandwidth in the image transmission. Unique image processing hardware, NASA's Programmable Remapper, allows demonstration of the method. Once refined, the technology could be adapted to special purpose imagers and display devices, or otherwise to dedicated image processing hardware.

Juday, Richard D.↗
NASA NTRS2008

Microshutter Arrays for NIRSpec

A primary science goal of the 6.5 m James Webb Space Telescope is to characterize the epoch of initial galaxy formation, observing the early universe as the first stars and galaxies formed. This program will be accomplished using a combination of multi-band imaging and spectroscopic measurements of large numbers of faint galaxies. Since these objects are in general sparse on the sky, a multi object spectrometer is required to enable this critical scientific investigation. We have developed a microshutter array which is to be used as a high contrast, remotely programmable field selector for the Near Infrared Spectrometer (NIRSpec) on JWST. This device allows slits to be opened at the locations of selected galaxies in the field of view, and blocks sources and background light from the rest of the field. The first flight design devices have been built and were tested. These first generation of devices were used to demonstrate performance and flight readiness. Devices of the same design will be delivered to ESA for installation into the NIRSpec instrument.

Silverberg, Robert↗
NASA NTRS2008

FPGA Control System for the Automated Test of Microshutters

The James Webb Space Telescope, scheduled to replace the Hubble in 2013, must simultaneously observe hundreds of faint galaxies. This requirement has led to the development of a programmable transmission mask which can be adapted to admit light with arbitrary pattern of galaxies into its spectrograph. This programmable mask will contain a large array of micro-electromechanical (MEMs) devices called MicroShutters. These microscopic shutters physically open and close like the shutter on a camera, except each shutter is microscopic in size and an array 365 by 171 is used to select the objects under spectroscopic observation at a given time, and to block the unwanted background light from other areas. NASA developed and is currently refining the exceptionally difficult process of manufacturing these shutters. This paper describes how the authors used LabVIEW FPGA and a reconfigurable I/O board to control the shutters in a test chamber and how the flexibility of the system allows us to continue to modify the control algorithms as NASA optimizes the performance of the MicroShutter arrays.

Lyness, Eric↗
NASA NTRS2008

FPGA Control System for the Automated Test of MicroShutters

The James Webb Space Telescope, scheduled to replace the Hubble in 2013, must simultaneously observe hundreds of faint galaxies. This requirement has led to the development of a programmable transmission mask which can be adapted to admit light from an arbitrary pattern of galaxies into its spectrograph. This programmable mask will contain a large array of micro-electromechanical (MEMs) devices called MicroShutters. These microscopic shutters physically open and close like the shutter on a camera, except each shutter is microscopic in size and an array 365 by 171 is used to select the objects under spectroscopic observation at a given time, and to block the unwanted background light from other areas. NASA developed and is currently refining the exceptionally difficult process of manufacturing these shutters. This paper describes how the authors used LabVIEW FPGA and a reconfigurable I/O board to control the shutters in a test chamber and how the flexibility of the system allows us to continue to modify the control algorithms as NASA optimizes the performance of the MicroShutter arrays.

Lyness, Eric↗
NASA NTRS2008

Column Grid Array Rework for High Reliability

Due to requirements for reduced size and weight, use of grid array packages in space applications has become common place. To meet the requirement of high reliability and high number of I/Os, ceramic column grid array packages (CCGA) were selected for major electronic components used in next MARS Rover mission (specifically high density Field Programmable Gate Arrays). ABSTRACT The probability of removal and replacement of these devices on the actual flight printed wiring board assemblies is deemed to be very high because of last minute discoveries in final test which will dictate changes in the firmware. The questions and challenges presented to the manufacturing organizations engaged in the production of high reliability electronic assemblies are, Is the reliability of the PWBA adversely affected by rework (removal and replacement) of the CGA package? and How many times can we rework the same board without destroying a pad or degrading the lifetime of the assembly? To answer these questions, the most complex printed wiring board assembly used by the project was chosen to be used as the test vehicle, the PWB was modified to provide a daisy chain pattern, and a number of bare PWB s were acquired to this modified design. Non-functional 624 pin CGA packages with internal daisy chained matching the pattern on the PWB were procured. The combination of the modified PWB and the daisy chained packages enables continuity measurements of every soldered contact during subsequent testing and thermal cycling. Several test vehicles boards were assembled, reworked and then thermal cycled to assess the reliability of the solder joints and board material including pads and traces near the CGA. The details of rework process and results of thermal cycling are presented in this paper.

high reliability↗
NASA NTRS2010

Methods and circuitry for reconfigurable SEU/SET tolerance

A device is disclosed in one embodiment that has multiple identical sets of programmable functional elements, programmable routing resources, and majority voters that correct errors. The voters accept a mode input for a redundancy mode and a split mode. In the redundancy mode, the programmable functional elements are identical and are programmed identically so the voters produce an output corresponding to the majority of inputs that agree. In a split mode, each voter selects a particular programmable functional element output as the output of the voter. Therefore, in the split mode, the programmable functional elements can perform different functions, operate independently, and/or be connected together to process different parts of the same problem.

Shuler, Jr., Robert L.↗
NASA NTRS2020

An Embedded Planar-Foil Capacitor Material, FPGA Based Interposer, Aimed at Improving System Performance and Reduced Board Size for Space Based Electronics

This paper presents our work to date in developing, and testing an embedded planar-foil capacitor based interposer intended to be integrated together with high-density components such as Field Programmable Gate Arrays (FPGAs), and Application Specific Integrated Circuit (ASIC) applications. FPGA devices typically have a large number of I/O and power pins. The high speed enabled by these devices requires a large number of discrete bypass capacitors as close as possible to the power pins. These capacitors take up a considerable amount of the board area on the application circuit board. Our interposer replaces these components freeing up space of traditional bypass capacitors for other circuitry. Our Interposer focuses on the needs of Micro Semi’s RTG4 FPGA. We developed the interposer using COTS embedded foil capacitors. The Interposer is customized to the capacitance requirements for each of the FPGA banks. We evaluated three foil manufactures Oak Mitsui, 3M and TDK. The three different designs were evaluated, but we will focus on the Oak-Mitsui based Interposer that we constructed and tested. Through simulations, we validate the horizontal and vertical interconnect inductances, that FPGA decoupling requirements are met. The use of the interposer results in an overall reduction in our Printed Wiring Board (PWB) area.

Hunter, Don J↗
NASA NTRS2009

Board Saver for Use with Developmental FPGAs

A device denoted a board saver has been developed as a means of reducing wear and tear of a printed-circuit board onto which an antifuse field programmable gate array (FPGA) is to be eventually soldered permanently after a number of design iterations. The need for the board saver or a similar device arises because (1) antifuse-FPGA design iterations are common and (2) repeated soldering and unsoldering of FPGAs on the printed-circuit board to accommodate design iterations can wear out the printed-circuit board. The board saver is basically a solderable/unsolderable FPGA receptacle that is installed temporarily on the printed-circuit board. The board saver is, more specifically, a smaller, square-ring-shaped, printed-circuit board (see figure) that contains half via holes one for each contact pad along its periphery. As initially fabricated, the board saver is a wider ring containing full via holes, but then it is milled along its outer edges, cutting the via holes in half and laterally exposing their interiors. The board saver is positioned in registration with the designated FPGA footprint and each via hole is soldered to the outer portion of the corresponding FPGA contact pad on the first-mentioned printed-circuit board. The via-hole/contact joints can be inspected visually and can be easily unsoldered later. The square hole in the middle of the board saver is sized to accommodate the FPGA, and the thickness of the board saver is the same as that of the FPGA. Hence, when a non-final FPGA is placed in the square hole, the combination of the non-final FPGA and the board saver occupy no more area and thickness than would a final FPGA soldered directly into its designated position on the first-mentioned circuit board. The contact leads of a non-final FPGA are not bent and are soldered, at the top of the board saver, to the corresponding via holes. A non-final FPGA can readily be unsoldered from the board saver and replaced by another one. Once the final FPGA design has been determined, the board saver can be unsoldered from the contact pads on the first-mentioned printed-circuit board and replaced by the final FPGA.

Berkun, Andrew↗
NASA NTRS1990

The design and proof of correctness of a fault-tolerant circuit

The flowing achievements are presented in view graph form: (1) a formal statement of interactive consistency conditions in the Boyer-Moore logic; (2) a formal statement of the oral messages (OM) algorithm in the Boyer-Moore logic; (3) a mechanically checked proof that OM satisfies the interactive consistency conditions; (4) a mechanically checked proof of the optimality result--no algorithm can tolerate fewer faults than OM yet still achieve interactive consistency; (5) the use of OM in a functional specification for a fault-tolerant device; (6) a formal description of the design of the device; (7) a mechanically checked proof that the device design satisfies the specification; and (8) an implementation of the design in programmable logic arrays.

Bevier, William R.↗
NASA NTRS2010

FPGA NEPP : FY09 summary report

This report documents the activities and results of the fiscal year 2009 (FY09) funding for the NASA Electronic Parts and Packaging (NEPP) program for re-programmable field programmable gate arrays (FPGAs). The FY09 task was divided into three efforts: 1. Device physics-based design modifications 2. Contention study of Xilinx Virtex-4 3. IDDQ study of Actel A54SX The FY09 NEPP FPGA study was organized into these three sections in recognition of the continued and increasing importance of FPGAs to NASA. FPGAs represent the state of the art in electronic components with millions and millions of transistors integrated into a single device. Modern NASA spacecraft design has dozens and dozens of FPGAs implemented onboard. FPGAs are used in critical command and data handling, instrument control and monitoring, and communications protocols, to name just a few. The reliability of FPGAs is fundamental to mission success for NASA.

Sheldon, Douglas↗
NASA NTRS1991

An electronic pan/tilt/zoom camera system

A camera system for omnidirectional image viewing applications that provides pan, tilt, zoom, and rotational orientation within a hemispherical field of view (FOV) using no moving parts was developed. The imaging device is based on the effect that from a fisheye lens, which produces a circular image of an entire hemispherical FOV, can be mathematically corrected using high speed electronic circuitry. An incoming fisheye image from any image acquisition source is captured in memory of the device, a transformation is performed for the viewing region of interest and viewing direction, and a corrected image is output as a video image signal for viewing, recording, or analysis. As a result, this device can accomplish the functions of pan, tilt, rotation, and zoom throughout a hemispherical FOV without the need for any mechanical mechanisms. A programmable transformation processor provides flexible control over viewing situations. Multiple images, each with different image magnifications and pan tilt rotation parameters, can be obtained from a single camera. The image transformation device can provide corrected images at frame rates compatible with RS-170 standard video equipment.

Zimmermann, Steve↗
NASA NTRS1981

Video image processor on the Spacelab 2 Solar Optical Universal Polarimeter /SL2 SOUP/

The SOUP instrument is designed to obtain diffraction-limited digital images of the sun with high photometric accuracy. The Video Processor originated from the requirement to provide onboard real-time image processing, both to reduce the telemetry rate and to provide meaningful video displays of scientific data to the payload crew. This original concept has evolved into a versatile digital processing system with a multitude of other uses in the SOUP program. The central element in the Video Processor design is a 16-bit central processing unit based on 2900 family bipolar bit-slice devices. All arithmetic, logical and I/O operations are under control of microprograms, stored in programmable read-only memory and initiated by commands from the LSI-11. Several functions of the Video Processor are described, including interface to the High Rate Multiplexer downlink, cosmetic and scientific data processing, scan conversion for crew displays, focus and exposure testing, and use as ground support equipment.

Lindgren, R. W.↗
NASA NTRS1985

Efficient implementation of real-time programs under the VAX/VMS operating system

Techniques for writing efficient real-time programs under the VAX/VMS oprating system are presented. Basic operations are presented for executing at real-time priority and for avoiding needlless processing delays. A highly efficient technique for accessing physical devices by mapping to the input/output space and accessing the device registrs directly is described. To illustrate the application of the technique, examples are included of different uses of the technique on three devices in the Langley Avionics Integration Research Lab (AIRLAB): the KW11-K dual programmable real-time clock, the Parallel Communications Link (PCL11-B) communication system, and the Datacom Synchronization Network. Timing data are included to demonstrate the performance improvements realized with these applications of the technique.

Johnson, S. C.↗
NASA NTRS1992

The locator system for wandering individuals

Configurations and operation strategies are described for a wanderer locator system based on wireless radio frequency communication designed to monitor elderly patients who may wander beyond safe perimeters in the home or in an institutional setting. The modular components of this wandering notification system are (1) portable transmitter/receivers to be worn or carried by the patient and the caretaker, (2) detectors to be mounted in doorways or other perimeters of a safe area, (3) programmable central processing units to control, communicate with, and/or trace the portable and remote devices, and (4) a cathode ray tube that can display information on patient location or system status. Photographs of all system components and illustrations of operations concepts are included.

Davidson, Shayla↗
NASA NTRS2011

NASA Tech Briefs, October 2011

Topics covered include: Laser Truss Sensor for Segmented Telescope Phasing; Qualifications of Bonding Process of Temperature Sensors to Deep-Space Missions; Optical Sensors for Monitoring Gamma and Neutron Radiation; Compliant Tactile Sensors; Cytometer on a Chip; Measuring Input Thresholds on an Existing Board; Scanning and Defocusing Properties of Microstrip Reflectarray Antennas; Cable Tester Box; Programmable Oscillator; Fault-Tolerant, Radiation-Hard DSP; Sub-Shot Noise Power Source for Microelectronics; Asynchronous Message Service Reference Implementation; Zero-Copy Objects System; Delay and Disruption Tolerant Networking MACHETE Model; Contact Graph Routing; Parallel Eclipse Project Checkout; Technique for Configuring an Actively Cooled Thermal Shield in a Flight System; Use of Additives to Improve Performance of Methyl Butyrate-Based Lithium-Ion Electrolytes; Li-Ion Cells Employing Electrolytes with Methyl Propionate and Ethyl Butyrate Co-Solvents; Improved Devices for Collecting Sweat for Chemical Analysis; Tissue Photolithography; Method for Impeding Degradation of Porous Silicon Structures; External Cooling Coupled to Reduced Extremity Pressure Device; A Zero-Gravity Cup for Drinking Beverages in Microgravity; Co-Flow Hollow Cathode Technology; Programmable Aperture with MEMS Microshutter Arrays; Polished Panel Optical Receiver for Simultaneous RF/Optical Telemetry with Large DSN Antennas; Adaptive System Modeling for Spacecraft Simulation; Lidar-Based Navigation Algorithm for Safe Lunar Landing; Tracking Object Existence From an Autonomous Patrol Vehicle; Rad-Hard, Miniaturized, Scalable, High-Voltage Switching Module for Power Applications; and Architecture for a 1-GHz Digital RADAR.

Source record↗
NASA NTRS2006

Single Event Effects Test Results for the Actel ProASIC Plus and Altera Stratix-II Field Programmable Gate Arrays

This work describes radiation testing of Actel's ProASIC Plus and Altera's Stratix-II FPGAs. The Actel Device Under Test (DUT) was a ProASIC Plus APA300-PQ208 nonvolatile, field reprogrammable device which is based on a 0.22micron flash-based LVCMOS technology. Limited investigation has taken place into flash based FPGA technologies, therefore this test served as a preliminary reference point for various SEE behaviors. The Altera DUT was a Stratix-II EP2S60F1020C4. Single Event Upset (SEU) and Single Event Latchup (SEL) were the focus of these studies. For the Actel, a latchup test was done at an effective LET of 75.0 MeV-sq cm/mg at room temperature, and no latchup was detected when irradiated to a total fluence of 1 x 10(exp 7) particles/sq cm. The Altera part was shown to latchup at room temperature.

heavy ions↗
NASA NTRS1987

CCD Memory

CCD memory device yields over 6.4 x 10 to the eighth power levels of information on single chip. Charge-coupled device (CCD) demonstrated to operate as either read-only-memory (ROM) or photon-programmable memory with capacity of 640,000 bits, with each bit capable of being weighted to more than 1,000 discrete analog levels. Larger memory capacities now possible using proposed approach in conjunction with CCD's now being fabricated, which yield over 4 x 10 to the ninth power discrete levels of information on single chip.

Janesick, James R.↗