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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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167 records · Page 10
All sourcesNASA NTRSDOE OSTI
DOE OSTI2026

Interface and Thermophysical Properties of R 32 Refrigerant

Driven by the urgent demand for efficient cooling in microelectronics and advanced thermal management systems, difluoromethane (R32/CH 2 F 2 ) has emerged as a promising candidate owing to its favorable thermophysical properties, including high heat transfer efficiency and low viscosity. While bulk properties such as density, viscosity, and thermal conductivity have been widely studied, interfacial properties, including surface tension and interfacial thickness, remain comparatively underexplored, despite their importance in phase-transition dynamics. Here, we perform molecular dynamics (MD) simulations from 180 to 300 K using an optimized transferable force field for fluoropropenes with enhanced electrostatics to assess both bulk and interfacial behavior of R32. Simulations reproduced density within ±2.1%, viscosity within 3.05%, and thermal conductivity within 7.41% of NIST reference data. Heat capacities (C p and C v ) were predicted within 5%. For interfacial properties, surface tension trends were reproduced within 13.58% deviation, and the vapor–liquid coexistence curve closely matched reference data, yielding a critical temperature of 345.7 K (1.6% deviation) and a critical density of 0.397 g/cm 3 (6.4% deviation). Importantly, the vapor–liquid interface exhibited pronounced temperature-dependent broadening across the 180–290 K range. This behavior correlates with increasing molecular kinetic energy, reduction in intermolecular cohesive interactions, and a progressive loss of preferential dipole alignment, which collectively enhance thermal fluctuation amplitudes at elevated temperatures. These validated results provide predictive molecular-level insights, particularly for interfacial properties that remain less characterized. By reducing property prediction errors in key parameters such as critical temperature, this work provides reliable inputs for heat-exchanger and system models. Such correlations can support optimized component sizing, improved performance, and reduced refrigerant charge. Beyond R32, the methodology offers a transferable framework for blended and next-generation low-GWP refrigerants, contributing to sustainable thermal management aligned with the 2027 EU F-Gas regulation and 2030 Kigali Amendment.

Fluids↗
DOE OSTI2025

3D nanolithography with metalens arrays and spatially adaptive illumination

The growing demand for advanced materials, miniaturized devices and integrated microsystems calls for the reliable fabrication of complex, multiscale, three-dimensional (3D) architectures, a need increasingly addressed through light-based and laser-based processes. However, owing to the field-of-view (FOV) limitations of conventional imaging optics, existing 3D laser nanofabrication techniques face fundamental challenges in throughput, proximity error and stitching defects on the path to scaling. Here, in this study, we present a scalable 3D nanofabrication platform that uses a metalens-generated focal spot array to parallelize two-photon lithography (TPL) beyond centimetre-scale write field areas. Metalenses are ideally suited for producing submicron-scale focal spots for high-throughput nanolithography, as they uniquely feature large numerical apertures (NAs), immersion media compatibility and large-scale manufacturability. We experimentally demonstrate a printing system that uses a 12-cm 2 metalens array to produce more than 120,000 cooperative focal spots, corresponding to a throughput exceeding 10 8 voxels s −1 . By programmatically patterning the focal spot array using a spatial light modulator (SLM), an adaptive parallel printing strategy is developed for precise greyscale linewidth modulation and choreographed printing of semiperiodic and fully aperiodic 3D geometries. We demonstrate parallel printing of replicated microstructures (>50 M microparticles per day), centimetre-scale 3D architectures with feature sizes down to 113 nm, and photonic and mechanical metamaterials. This work demonstrates the potential of 3D nanolithography towards wafer-scale production, showing how TPL could be used at scale for applications in microelectronics, biomedicine, quantum technology and high-energy laser targets.

Materials science↗
NASA NTRS2000

Assessment and Assurance of Microelectronics Packaging Technology of Microelectromechanical Systems (MEMS)

Microelectromechanical systems (MEMS) have shown a significant promise in the last decade for a variety of applications such as air-bag, pressure sensors, accelerometer, microgyro, etc. Standard semiconductor microelectronics packaging needs the integrated circuits to be protected from the harsh environment, and provide electrical communication with the other parts of the circuit, facilitate thermal dissipation efficiently, and impart mechanical strength to the silicon die. Microelectronics packaging involves wafer dicing, bonding, lead attachment, encapsulation to protect from the environment, electrical integrity, and package leak tests to assure the packaging technology. In the case of MEMS the microstructures (active elements) often interfaces with the hostile environment where packaging leak tests and testing of such devices using chemical and mechanical parameters will be very difficult and expensive. Packaging of MEMS is significantly complex as they serve to protect from the environment and microstructures interact with the same environment to measure or affect the desired physical or chemical parameters. The most of the silicon circuitry is sensitive to temperature, moisture, magnetic field, light, and electromagnetic interference. The package must then protect the on-board silicon circuitry while simultaneously exposing the microsensor to the effect it 'measures to assure the MEMS technology by lowering the risk to zero. MEMS technology has a major application in developing a microspacecraft for space systems provided assurance of MEMS technology is sufficiently addressed nondestructively. This technology would eventually miniaturize many of the components of the spacecraft to reach the NASA's safety and mission assurance goal by building faster, cheaper, better, smaller spacecraft to explore the space more effectively by teaming-up with the other NASA centers using the limited resources available. This paper discusses the latest developments in the MEMS technology and challenging issues in the packaging of hermetically sealed and non-hermetically sealed MEMS sensor devices based on silicon, poly-silicon, and other materials for microspacecraft applications considering the space environment and reliability assurance qualification guidelines in perspective. Acknowledgments: The above research work is supported by the NASA Electronics Parts and Packaging Program (NEPP) and performed by the Jet Propulsion Laboratory, California Institute of Technology, Pasadena, CA under a contract with the NASA - Code Q for the Office of Safety and Mission Assurance Program 323-79.

Ramesham, Rajeshuni↗
DOE OSTI2019

Gas Ingress and Egress of MEMS Multi-Chip Modules and MEMS Devices

Hermetic microcircuit packaging was the dominant method of protecting semiconductor devices in the 1960s and 1970s. After losing majority market sectors to plastic encapsulated microelectronics over the last a few decades, hermetic packaging remains the preferred method of protecting semiconductor devices for critical applications such as in military, space, and medical fields, where components and systems are required to serve for several decades. MEMS devices impose additional challenges to packaging by requiring specific internal cavity pressures to function properly or deliver the needed quality (Q) factors. In MEMS multichip modules, internal pressure requirement conflicts arise when different MEMS devices require different internal gases and pressures. The authors developed a closed-formed equation to model pressure changes of hermetic enclosures due to gas ingression. This article expands the authors mathematical model to calculate gas pressure of a MEMS multichip module package as well as those of MEMS devices inside the multichip module package. These equations are not only capable of calculating service lifetimes of MEMS devices and multi-chip modules but can also help develop MEMS device packaging strategies to extend the service life of MEMS multi-chip modules.

36 MATERIALS SCIENCE↗
NASA NTRS1994

A combined electron beam/optical lithography process step for the fabrication of sub-half-micron-gate-length MMIC chips

Advanced radar and communication systems rely heavily on state-of-the-art microelectronics. Systems such as the phased-array radar require many transmit/receive (T/R) modules which are made up of many millimeter wave - microwave integrated circuits (MMIC's). The heart of a MMIC chip is the Gallium Arsenide (GaAs) field-effect transistor (FET). The transistor gate length is the critical feature that determines the operating frequency of the radar system. A smaller gate length will typically result in a higher frequency. In order to make a phased array radar system economically feasible, manufacturers must be capable of producing very large quantities of small-gate-length MMIC chips at a relatively low cost per chip. This requires the processing of a large number of wafers with a large number of chips per wafer, minimum processing time, and a very high chip yield. One of the bottlenecks in the fabrication of MIMIC chips is the transistor gate definition. The definition of sub-half-micron gates for GaAs-based field-effect transistors is generally performed by direct-write electron beam lithography (EBL). Because of the throughput limitations of EBL, the gate-layer fabrication is conventionally divided into two lithographic processes where EBL is used to generate the gate fingers and optical lithography is used to generate the large-area gate pads and interconnects. As a result, two complete sequences of resist application, exposure, development, metallization and lift-off are required for the entire gate structure. We have baselined a hybrid process, referred to as EBOL (electron beam/optical lithography), in which a single application of a multi-level resist is used for both exposures. The entire gate structure, (gate fingers, interconnects and pads), is then formed with a single metallization and lift-off process. The EBOL process thus retains the advantages of the high-resolution E-beam lithography and the high throughput of optical lithography while essentially eliminating an entire lithography/metallization/lift-off process sequence. This technique has been proven to be reliable for both trapezoidal and mushroom gates and has been successfully applied to metal-semiconductor and high-electron-mobility field-effect transistor (MESFET and HEMT) wafers containing devices with gate lengths down to 0.10 micron and 75 x 75 micron gate pads. The yields and throughput of these wafers have been very high with no loss in device performance. We will discuss the entire EBOL process technology including the multilayer resist structure, exposure conditions, process sensitivities, metal edge definition, device results, comparison to the standard gate-layer process, and its suitability for manufacturing.

Sewell, James S.↗