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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 181 records · Page 10
All sourcesNASA NTRSDOE OSTI
NASA NTRS1988

A parallel householder tridiagonalization stratagem using scattered row decomposition

Householder's method for tridiagonalizing a real symmetric matrix, a major step in evaluating eigenvalues of the matrix, is modified into a parallel algorithm for a concurrent machine of message passing type. Each processor of the concurrent machine has its own CPU, communications control and local memory. Messages are passed through connections between processors. Although the basic algorithm is inherently serial, the computations can be spread over all processors by scattering different rows of the matrix into processors, hence the term 'Scattered Row Decomposition'. The steps in the serial and the parallel algorithms are identified. Expressions for efficiency and speedup are given in terms of problem and machine parameters. For a concurrent machine of ring type interconnection, a selected representative problem of large order exhibits efficiency approaching 66 per cent.

Chang, H. Y.↗
NASA NTRS1998

Aeroservoelastic and Structural Dynamics Research on Smart Structures Conducted at NASA Langley Research Center

An overview of smart structures research currently underway at the NASA Langley Research Center in the areas of aeroservoelasticity and structural dynamics is presented. Analytical and experimental results, plans, potential technology pay-offs, and challenges are discussed. The goal of this research is to develop the enabling technologies to actively and passively control aircraft and rotorcraft vibration and loads using smart devices. These enabling technologies and related research efforts include developing experimentally-validated finite element and aeroservoelastic modeling techniques; conducting bench experimental tests to assess feasibility and understand system trade-offs; and conducting large-scale wind- tunnel tests to demonstrate system performance. The key aeroservoelastic applications of this research include: active twist control of rotor blades using interdigitated electrode piezoelectric composites and active control of flutter, and gust and buffeting responses using discrete piezoelectric patches. In addition, NASA Langley is an active participant in the DARPA/ Air Force Research Laboratory/ NASA/ Northrop Grumman Smart Wing program which is assessing aerodynamic performance benefits using smart materials. Keywords: aeroelasticity, smart structures, piezoelectric actuators, active fiber composites, rotorcraft, buffet load alleviation, individual blade control, aeroservoelasticity, shape memory alloys, damping augmentation, piezoelectric power consumption

McGowan, Anna-Maria Rivas↗
NASA NTRS2010

Ethernet-Enabled Power and Communication Module for Embedded Processors

The power and communications module is a printed circuit board (PCB) that has the capability of providing power to an embedded processor and converting Ethernet packets into serial data to transfer to the processor. The purpose of the new design is to address the shortcomings of previous designs, including limited bandwidth and program memory, lack of control over packet processing, and lack of support for timing synchronization. The new design of the module creates a robust serial-to-Ethernet conversion that is powered using the existing Ethernet cable. This innovation has a small form factor that allows it to power processors and transducers with minimal space requirements.

Perotti, Jose↗
NASA NTRS2016

High Data Rate Architecture (HiDRA)

One of the greatest challenges in developing new space technology is in navigating the transition from ground based laboratory demonstration at Technology Readiness Level 6 (TRL-6) to conducting a prototype demonstration in space (TRL-7). This challenge is com- pounded by the relatively low availability of new spacecraft missions when compared with aeronautical craft to bridge this gap, leading to the general adoption of a low-risk stance by mission management to accept new, unproven technologies into the system. Also in consideration of risk, the limited selection and availability of proven space-grade components imparts a severe limitation on achieving high performance systems by current terrestrial technology standards. Finally from a space communications point of view the long duration characteristic of most missions imparts a major constraint on the entire space and ground network architecture, since any new technologies introduced into the system would have to be compliant with the duration of the currently deployed operational technologies, and in some cases may be limited by surrounding legacy capabilities. Beyond ensuring that the new technology is verified to function correctly and validated to meet the needs of the end users the formidable challenge then grows to additionally include: carefully timing the maturity path of the new technology to coincide with a feasible and accepting future mission so it flies before its relevancy has passed, utilizing a limited catalog of available components to their maximum potential to create meaningful and unprecedented new capabilities, designing and ensuring interoperability with aging space and ground infrastructures while simultaneously providing a growth path to the future. The International Space Station (ISS) is approaching 20 years of age. To keep the ISS relevant, technology upgrades are continuously taking place. Regarding communications, the state-of-the-art communication system upgrades underway include high-rate laser terminals. These must interface with the existing, aging data infrastructure. The High Data Rate Architecture (HiDRA) project is designed to provide networked store, carry, and forward capability to optimize data flow through both the existing radio frequency (RF) and new laser communications terminal. The networking capability is realized through the Delay Tolerant Networking (DTN) protocol, and is used for scheduling data movement as well as optimizing the performance of existing RF channels. HiDRA is realized as a distributed FPGA memory and interface controller that is itself controlled by a local computer running DTN software. Thus HiDRA is applicable to other arenas seeking to employ next-generation communications technologies, e.g. deep space. In this paper, we describe HiDRA and its far-reaching research implications.

DTN↗
NASA NTRS2017

On the Development and Application of High Data Rate Architecture (HiDRA) in Future Space Networks

Historically, space missions have been severely constrained by their ability to downlink the data they have collected. These constraints are a result of relatively low link rates on the spacecraft as well as limitations on the time during which data can be sent. As part of a coherent strategy to address existing limitations and get more data to the ground more quickly, the Space Communications and Navigation (SCaN) program has been developing an architecture for a future solar system Internet. The High Data Rate Architecture (HiDRA) project is designed to fit into such a future SCaN network. HiDRA's goal is to describe a general packet-based networking capability which can be used to provide assets with efficient networking capabilities while simultaneously reducing the capital costs and operational costs of developing and flying future space systems.Along these lines, this paper begins by reviewing various characteristics of modern satellite design as well as relevant characteristics of emerging technologies (such as free-space optical links capable of working at 100+ Gbps). Next, the paper describes HiDRA's design, and how the system is able to both integrate and support the operation of not only today's high-rate systems, but also the high-rate systems likely to be found in the future. This section also explores both existing and future networking technologies, such as Delay Tolerant Networking (DTN) protocol (RFC4838 citeRFC:1, RFC5050citeRFC:2), and explains how HiDRA supports them. Additionally, this section explores how HiDRA is used for scheduling data movement through both proactive and reactive link management. After this, the paper moves on to explore a reference implementation of HiDRA. This implementation is currently being realized based on a Field Programmable Gate Array (FPGA) memory and interface controller that is itself controlled by a local computer running DTN software. Next, this paper explores HiDRA's natural evolution, which includes an integration path for software-defined networking (SDN) switches. This section also describes considerations for both near-Earth and deep-space instantiations of HiDRA, describing how differences in latencies between the environments will necessarily influence how the system is configured and the networks operate. Finally, this paper describes future work. This section includes a description of a potential ISS implementation which will allow rapid advancement through the technology readiness levels (TRL). This section also explores work being done to support HiDRA's successful implementation and operation in a heterogeneous network: such a network could include communications equipment spanning many vintages and capabilities, and one significant aspect of HiDRA's future development involves balancing compatibility with capability.

DTN↗
NASA NTRSDate not supplied

Overview of Results from the MISSE 9-15 Polymers and Composites Experiment 1-4 (PCE 1-4)

Spacecraft in low Earth orbit (LEO) and other planetary orbits are subjected to harsh environmental conditions that can result in erosion, embrittlement and optical property degradation of susceptible materials threatening spacecraft performance and durability. To increase our understanding of space environmental effects on spacecraft materials, NASA Glenn Research Center has developed a series of experiments flown as part of the Materials International Space Station Experiment (MISSE) missions on the exterior of the International Space Station (ISS). Four Glenn experiments with 365 flight samples were flown on ISS’s MISSE-Flight Facility (MISSE-FF). These experiments are the Polymers and Composites Experiment-1 (PCE-1) flown as part of the MISSE-9 mission, the PCE-2 flown as part of the MISSE-10 mission, the PCE-3 flown as part of the MISSE-12 and MISSE-15 missions, and the PCE-4 flown as part of the MISSE-13 mission. The PCE 1-4 flight samples were flown in either ram, wake, zenith or nadir flight orientations. The primary objectives of the PCE 1-4 experiments are to determine the LEO atomic oxygen (AO) erosion yield, Ey (volume loss per incident oxygen atom) and radiation durability of spacecraft polymers, composites and coatings. In addition, each experiment has a wide variety of materials with numerous sample objectives. This presentation provides an overview of the PCE 1-4 experiments, the numerous sample collaborators, the space environmental exposure of the flight samples, and an overview of the post-flight observations and results. The results include AO fluence and contamination analyses for each mission flight orientation, erosion data for the PCE 1-4 AO Ey samples, optical property data, and tensile results for the MISSE-9 and MISSE-13 tensile samples. In addition, an introduction of results from other unique samples such as indium tin oxide (ITO) coated thermal control samples, shape memory polymer composites, melanin based composites, and specialty coatings, will be provided.

Atomic oxygen↗
DOE OSTI2020

Method and apparatus for maintaining data coherence in a non-uniform compute device

A data processing apparatus includes one or more host processors with first processing units, one or more caches with second processing unit, a non-cache memory having a third processing unit and a reorder buffer operable to maintain data order during execution of a program of instructions. An instruction scheduler routes instructions to the processing units. Data coherence is maintained by control logic that blocks access to data locations in use by a selected processing unit other than the selected processing unit until data associated with the data locations are released from the reorder buffer. Data stored in the cache is written to the memory if it is already in a modified state, otherwise the state is set to the modified state. A memory controller may be used to restrict access to memory locations to be operated on.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS1996

Active Vibration Control of Elastic Beam by Means of Shape Memory Alloy Layers

The mathematical model of a flexible beam covered with shape memory alloy (SMA) layers is presented. The SMA layers are used as actuators, which are capable of changing their elastic modulus and recovery stress, thus changing the natural frequency of, and adjusting the excitation to, the vibrating beam. The frequency factor variation as a function of SMA Young's modulus, SMA layer thickness and beam thickness is discussed. Also control of the beam employing an optimal linear control law is evaluated. The control results indicate how the system reacts to various levels of excitation input through the non-homogeneous recovery shear term of the governing differential equation.

Chen, Q.↗
NASA NTRS2002

Memory-Intensive Benchmarks: IRAM vs. Cache-Based Machines

The increasing gap between processor and memory performance has lead to new architectural models for memory-intensive applications. In this paper, we explore the performance of a set of memory-intensive benchmarks and use them to compare the performance of conventional cache-based microprocessors to a mixed logic and DRAM processor called VIRAM. The benchmarks are based on problem statements, rather than specific implementations, and in each case we explore the fundamental hardware requirements of the problem, as well as alternative algorithms and data structures that can help expose fine-grained parallelism or simplify memory access patterns. The benchmarks are characterized by their memory access patterns, their basic control structures, and the ratio of computation to memory operation.

Biswas, Rupak↗
NASA NTRS1982

Array processor architecture connection network

A connection network is disclosed for use between a parallel array of processors and a parallel array of memory modules for establishing non-conflicting data communications paths between requested memory modules and requesting processors. The connection network includes a plurality of switching elements interposed between the processor array and the memory modules array in an Omega networking architecture. Each switching element includes a first and a second processor side port, a first and a second memory module side port, and control logic circuitry for providing data connections between the first and second processor ports and the first and second memory module ports. The control logic circuitry includes strobe logic for examining data arriving at the first and the second processor ports to indicate when the data arriving is requesting data from a requesting processor to a requested memory module. Further, connection circuitry is associated with the strobe logic for examining requesting data arriving at the first and the second processor ports for providing a data connection therefrom to the first and the second memory module ports in response thereto when the data connection so provided does not conflict with a pre-established data connection currently in use.

Barnes, George H.↗
NASA NTRS2004

Hold-up power supply for flash memory

A hold-up power supply for flash memory systems is provided. The hold-up power supply provides the flash memory with the power needed to temporarily operate when a power loss exists. This allows the flash memory system to complete any erasures and writes, and thus allows it to shut down gracefully. The hold-up power supply detects when a power loss on a power supply bus is occurring and supplies the power needed for the flash memory system to temporally operate. The hold-up power supply stores power in at least one capacitor. During normal operation, power from a high voltage supply bus is used to charge the storage capacitors. When a power supply loss is detected, the power supply bus is disconnected from the flash memory system. A hold-up controller controls the power flow from the storage capacitors to the flash memory system. The hold-up controller uses feedback to assure that the proper voltage is provided from the storage capacitors to the flash memory system. This power supplied by the storage capacitors allows the flash memory system to complete any erasures and writes, and thus allows the flash memory system to shut down gracefully.

Ott, William E.↗
NASA NTRS1988

Programmable control means for providing safe and controlled medication infusion

An implantable programmable infusion pump (IPIP) is disclosed and generally includes: a fluid reservoir filled with selected medication; a pump for causing a precise volumetric dosage of medication to be withdrawn from the reservoir and delivered to the appropriate site within the body; and, a control means for actuating the pump in a safe and programmable manner. The control means includes a microprocessor, a permanent memory containing a series of fixed software instructions, and a memory for storing prescription schedules, dosage limits and other data. The microprocessor actuates the pump in accordance with programmable prescription parameters and dosage limits stored in the memory. A communication link allows the control means to be remotely programmed. The control means incorporates a running integral dosage limit and other safety features which prevent an inadvertent or intentional medication overdose. The control means also monitors the pump and fluid handling system and provides an alert if any improper or potentially unsafe operation is detected.

Fischell, Robert E.↗
DOE OSTI2020

Phase control of coherent acoustic phonons in gold bipyramids for optical memory and manipulating plasmon–exciton coupling

Recent efforts have targeted manipulation of nanomaterial vibrational modes in applications such as chemical/mass sensing, optical switching, and phonon-driven photochemistry. While impulsive photoexcitation can generate coherent phonons, multiple excitation pulses offer the prospect of control and manipulation of coherent phonon modes for functions of optical memory and logic. In this work, we use such an approach to inject an arbitrary coherent phonon phase into a colloidal ensemble of highly monodisperse gold bipyramids. We then demonstrate that this technique can be applied to a system that exhibits plasmon-exciton coupling to further manipulate the hybridization of the system. This ability to manipulate acoustic phonons and hybridization can enable optical logic applications of acoustic phonons in addition to optical memory.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2022

Control of a Three-Phase Grid-Connected Voltage-Sourced Converter Using Long Short-Term Memory Networks

With the rise of inverter-based resources (IBRs) within the power system, the control of grid-connected converters (GCCs) has become pertinent due to the fact they interface IBRs to the grid. The conventional method of control for a GCC such as the voltage-sourced converter (VSC) is through a decoupled control loop in the synchronous reference frame. However, this model-based control method is sensitive to parameter changes causing deterioration in controller performance. Data-driven approaches such as machine learning can be utilized to design controllers that are capable of operating GCCs in various system conditions. This work explores a deep learning-based control method for a three-phase grid-connected VSC, specifically utilizing a long short-term memory (LSTM) network for robust control. Simulations of a conventional controlled VSC are conducted using Simulink to collect data for training the LSTM-based controller. The LSTM model is built and trained using the Keras and TensorFlow libraries in Python and tested in Simulink. The performance of the LSTM-based controller is evaluated under different case studies and compared to the conventional method of control. Simulation results demonstrate the effectiveness of this approach by outperforming the conventional controller and maintaining stability under different system parameter changes.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS1993

System for simultaneously loading program to master computer memory devices and corresponding slave computer memory devices

A bus programmable slave module card for use in a computer control system is disclosed which comprises a master computer and one or more slave computer modules interfacing by means of a bus. Each slave module includes its own microprocessor, memory, and control program for acting as a single loop controller. The slave card includes a plurality of memory means (S1, S2...) corresponding to a like plurality of memory devices (C1, C2...) in the master computer, for each slave memory means its own communication lines connectable through the bus with memory communication lines of an associated memory device in the master computer, and a one-way electronic door which is switchable to either a closed condition or a one-way open condition. With the door closed, communication lines between master computer memory (C1, C2...) and slave memory (S1, S2...) are blocked. In the one-way open condition invention, the memory communication lines or each slave memory means (S1, S2...) connect with the memory communication lines of its associated memory device (C1, C2...) in the master computer, and the memory devices (C1, C2...) of the master computer and slave card are electrically parallel such that information seen by the master's memory is also seen by the slave's memory. The slave card is also connectable to a switch for electronically removing the slave microprocessor from the system. With the master computer and the slave card in programming mode relationship, and the slave microprocessor electronically removed from the system, loading a program in the memory devices (C1, C2...) of the master accomplishes a parallel loading into the memory devices (S1, S2...) of the slave.

Hall, William A.↗
NASA NTRS2004

FPGA-Based, Self-Checking, Fault-Tolerant Computers

A proposed computer architecture would exploit the capabilities of commercially available field-programmable gate arrays (FPGAs) to enable computers to detect and recover from bit errors. The main purpose of the proposed architecture is to enable fault-tolerant computing in the presence of single-event upsets (SEUs). [An SEU is a spurious bit flip (also called a soft error) caused by a single impact of ionizing radiation.] The architecture would also enable recovery from some soft errors caused by electrical transients and, to some extent, from intermittent and permanent (hard) errors caused by aging of electronic components. A typical FPGA of the current generation contains one or more complete processor cores, memories, and highspeed serial input/output (I/O) channels, making it possible to shrink a board-level processor node to a single integrated-circuit chip. Custom, highly efficient microcontrollers, general-purpose computers, custom I/O processors, and signal processors can be rapidly and efficiently implemented by use of FPGAs. Unfortunately, FPGAs are susceptible to SEUs. Prior efforts to mitigate the effects of SEUs have yielded solutions that degrade performance of the system and require support from external hardware and software. In comparison with other fault-tolerant- computing architectures (e.g., triple modular redundancy), the proposed architecture could be implemented with less circuitry and lower power demand. Moreover, the fault-tolerant computing functions would require only minimal support from circuitry outside the central processing units (CPUs) of computers, would not require any software support, and would be largely transparent to software and to other computer hardware. There would be two types of modules: a self-checking processor module and a memory system (see figure). The self-checking processor module would be implemented on a single FPGA and would be capable of detecting its own internal errors. It would contain two CPUs executing identical programs in lock step, with comparison of their outputs to detect errors. It would also contain various cache local memory circuits, communication circuits, and configurable special-purpose processors that would use self-checking checkers. (The basic principle of the self-checking checker method is to utilize logic circuitry that generates error signals whenever there is an error in either the checker or the circuit being checked.) The memory system would comprise a main memory and a hardware-controlled check-pointing system (CPS) based on a buffer memory denoted the recovery cache. The main memory would contain random-access memory (RAM) chips and FPGAs that would, in addition to everything else, implement double-error-detecting and single-error-correcting memory functions to enable recovery from single-bit errors.

Some, Raphael↗