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All sources NASA NTRS DOE OSTI

DOE OSTI2020

Understanding the Impact of Memory Access Patterns in Intel Processors

Because of increasing complexity in the memory hierarchy, predicting the performance of a given application in a given processor is becoming more difficult. The problem is worsened by the fact that the hardware needed to deal with more complex memory traffic also affects energy consumption. Moreover, in a heterogeneous system with shared main memory, the memory traffic between the last level cache (LLC) and the memory creates contention between other processors and accelerator devices. For these reasons, it is important to investigate and understand the impact of different memory access patterns on the memory system. This study investigates the interplay between Intel processors' memory hierarchy and different memory access patterns in applications. The authors explore sequential streaming and strided memory access patterns with the objective of predicting LLC-dynamic random access memory (DRAM) traffic for a given application in given Intel architectures. Moreover, the impact of prefetching is also investigated in this study. Experiments with different Intel micro-architectures uncover mechanisms to predict LLC-DRAM traffic that can yield up to 99% accuracy for sequential streaming access patterns and up to 95% accuracy for strided access patterns.

Alaul haque monil, Mohammad↗

DOE OSTI2015

Effects of non-invasive brain stimulation on associative memory

Associative memory refers to remembering the association between two items, such as a face and a name. It is a crucial part of daily life, but it is also one of the first aspects of memory performance that is impacted by aging and by Alzheimer’s disease. Evidence suggests that transcranial direct current stimulation (tDCS) can improve memory performance, but few tDCS studies have investigated its impact on associative memory. In addition, no prior study of the effects of tDCS on memory performance has systematically evaluated the impact of tDCS on different types of memory assessments, such as recognition and recall tests. In this study, we measured the effects of tDCS on associative memory performance in healthy adults, using both recognition and recall tests. Participants studied face-name pairs while receiving either active (30 minutes, 2 mA) or sham (30 minutes, 0.1 mA) stimulation with the anode placed at F9 and the cathode placed on the contralateral upper arm. Participants in the active stimulation group performed significantly better on the recall test than participants in the sham group, recalling 50% more names, on average, and making fewer recall errors. However, the two groups did not differ significantly in terms of their performance on the recognition memory test. This investigation provides evidence that stimulation at the time of study improves associative memory encoding, but that this memory benefit is evident only under certain retrieval conditions.

60 APPLIED LIFE SCIENCES↗

DOE OSTI2022

A Double-Edged Sword: The Role of Prior Knowledge in Memory Aging

People accumulate knowledge throughout their lifespan and the accumulated knowledge influences how we encode and retrieve information in memory processing. This study aims to investigate the role of knowledge in associative memory across the adult lifespan, and specifically examines the effects of two material properties that interact with prior knowledge: congruency – whether the material is congruent with people’s prior knowledge, and ambiguity – whether the material is ambiguous to interpret based on prior knowledge. 273 participants (aged 22–70 years old) completed an incidental memory task online. Participants were shown pictures depicting an object in a scene and judged if the object was likely or unlikely to be in the particular scene. Later, in the recognition test, participants were asked to identify if the exact picture was presented earlier. The pictures were manipulated to have varying levels of congruency, meaning that some depicted likely object–scene pairs and some unlikely. We also measured how different the likely/unlikely judgment for each object–scene pair was across all participants to determine the ambiguity level of the object–scene pair: some were more likely to receive diverse responses across people, whereas others are unambiguously consistent (or inconsistent) with common knowledge shared by most people. We used mixed-effects logistic regressions to predict memory outcome for each trial as a function of age, age 2 , congruency/ambiguity, and their interactions. The object–scene pairs perceived as congruent had higher hit rates than incongruent ones, as well as higher false alarm rates, especially in middle-aged and older people. Higher ambiguity was also related to both greater true and false memory, independent of age. Finally, the effect of ambiguity only emerged when the object–scene pair was perceived incongruent. The results suggest that people rely on prior knowledge to process new information and that this reliance improves hit responses, but also induces false memories particularly for middle-aged and older people, suggesting a double-edged role of knowledge in associative memory and its disproportionate influence on memory aging. Over-reliance on knowledge in older adults, which has been suspected in other cognitive processes, may be one of the mechanisms underlying associative memory decrease in aging.

60 APPLIED LIFE SCIENCES↗

DOE OSTI2021

Non-Markovian dynamics of open quantum system with memory

Highlights: • Non-Markovian master equation for open quantum system with power-law memory is proposed. • Non-Markovian dynamics of two-level quantum system with memory is described. • Solutions of non-Markovian quantum master equations are derived. • Complete positivity and bi-positivity in non-Markovian quantum dynamics with memory are described. • Exact solution of non-Markovian equations of system with memory is proposed. In this paper, non-Markovian generalization of master equation for open quantum system is proposed. Non-Markovian dynamics of two-level quantum system with memory and interaction with environment is described. To describe this system, the Gorini–Kossakowski–Sudarshan equation for open quantum states is generalized by taking into account power-law fading memory. The non-Markovian quantum processes with power-law memory are described by using integration and differentiation of non-integer orders. Complete positivity and bi-positivity in non-Markovian quantum dynamics with memory are described. An example of two-level quantum systems with power-law memory is suggested. Exact solution of the non-Markovian master equations of two-level open quantum systems with memory is derived.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2017

Bisphenol A impairs the memory function and glutamatergic homeostasis in a sex-dependent manner in mice: Beneficial effects of diphenyl diselenide

Bisphenol A (BPA) is a compound integrated in commodities, which consequently increases the human exposure to this toxicant. The deleterious effects of BPA exposure during periods of brain development have been documented mainly concerning the impairment in memory functions. Diphenyl diselenide (PhSe){sub 2}, an organoselenium compound, shows protective/restorative effects against memory deficits in experimental models. Thus, this study investigated the effects of (PhSe){sub 2} on the memory impairments induced by BPA exposure to male and female mice and the possible involvement of glutamatergic system in these effects. Three-week-old male and female Swiss mice received BPA (5 mg/kg), intragastrically, from 21st to 60th postnatal day. After, the animals were intragastrically treated with (PhSe){sub 2} (1 mg/kg) during seven days. The mice performed the behavioral memory tests and the [{sup 3}H] glutamate uptake and NMDA receptor subunits (2A and 2B) analyses were carried out in the hippocampus and cerebral cortex of mice. The results demonstrated that the BPA exposure induced impairment of object recognition memory in both sexes. However, it caused impairments in spatial memory in female and in the passive avoidance memory in male mice. Besides, BPA caused a decrease in the [{sup 3}H] glutamate uptake and NMDA receptor subunit levels in the cortical and hippocampal regions depending on the sex. Treatment with (PhSe){sub 2} reversed in a sex-independent manner the behavioral impairments and molecular alterations. In conclusion, BPA had a negative effect in different memory types as well as in the glutamatergic parameters in a sex-dependent manner and (PhSe){sub 2} treatment was effective against these alterations. - Highlights: • BPA exposure induced memory impairment in a sex dependent manner in mice. • (PhSe){sub 2} reversed memory impairments caused by BPA exposure in mice. • (PhSe){sub 2} modulated hippocampal and cortical [{sup 3}H]glutamate uptake in mice. • (PhSe){sub 2} restored the hippocampal and cortical NMDA receptor subunits levels.

60 APPLIED LIFE SCIENCES↗

DOE OSTI2021

Performance of CUDA Unified Memory in CMS Heterogeneous Pixel Reconstruction

The management of separate memory spaces of CPUs and GPUs brings an additional burden to the development of software for GPUs. To help with this, CUDA unified memory provides a single address space that can be accessed from both CPU and GPU. The automatic data transfer mechanism is based on page faults generated by the memory accesses. This mechanism has a performance cost, that can be with explicit memory prefetch requests. Various hints on the inteded usage of the memory regions can also be given to further improve the performance. The overall effect of unified memory compared to an explicit memory management can depend heavily on the application. In this paper we evaluate the performance impact of CUDA unified memory using the heterogeneous pixel reconstruction code from the CMS experiment as a realistic use case of a GPU-targeting HEP reconstruction software. We also compare the programming model using CUDA unified memory to the explicit management of separate CPU and GPU memory spaces.

Kortelainen, Matti J.↗

DOE OSTI2019

Thread Batching for High-performance Energy-efficient GPU Memory Design

Massive multi-threading in GPU imposes tremendous pressure on memory subsystems. Due to rapid growth in thread-level parallelism of GPU and slowly improved peak memory bandwidth, memory becomes a bottleneck of GPU’s performance and energy efficiency. In this article, we propose an integrated architectural scheme to optimize the memory accesses and therefore boost the performance and energy efficiency of GPU. First, we propose a thread batch enabled memory partitioning (TEMP) to improve GPU memory access parallelism. In particular, TEMP groups multiple thread blocks that share the same set of pages into a thread batch and applies a page coloring mechanism to bound each stream multiprocessor (SM) to the dedicated memory banks. After that, TEMP dispatches the thread batch to an SM to ensure high-parallel memory-access streaming from the different thread blocks. Second, a thread batch-aware scheduling (TBAS) scheme is introduced to improve the GPU memory access locality and to reduce the contention on memory controllers and interconnection networks. Experimental results show that the integration of TEMP and TBAS can achieve up to 10.3% performance improvement and 11.3% DRAM energy reduction across diverse GPU applications. We also evaluate the performance interference of the mixed CPU+GPU workloads when they are run on a heterogeneous system that employs our proposed schemes. Our results show that a simple solution can effectively ensure the efficient execution of both GPU and CPU applications.

Computer Science↗

DOE OSTI2019

Evaluating the effectiveness of program data features for guiding memory management

Recent trends have led to the adoption of larger and more complex memory systems, often with multiple tiers of memory performance within the same platform. To utilize complex memory systems efficiently, current data management strategies must be altered to map usage demands to the underlying hardware. Applications, as the generators of memory accesses, are well-suited to guide this process, but building and maintaining separate source code versions for different memory systems is not feasible in most cases. One potential solution is to employ automated program profiling and analysis to facilitate the production of application-based guidance. By attaching memory usage information to static or lightweight program features, compilers and runtime systems can generate fine-grained guidance without additional efforts from users or developers. Recent works have employed this approach with some success, but it is not clear which program features are most useful for guiding data management.This work evaluates the effectiveness of using different program data features to predict memory usage and guide memory management. It employs a custom set of simulation tools, based in the Intel® Pin framework, to collect and analyze the usage characteristics of application data associated with common program data features, such as allocation sites, types, and context. The results show that even relatively simple features, such as object size, are useful for selecting data with similar usage properties, but finer-grained features, such as the instructions that access a particular object, are often much more effective. Additionally, this work evaluates the performance of using different data features and different program inputs to guide data placement on a heterogeneous memory platform with a limited amount of high performance memory.

Effler, T. Chad↗

DOE OSTI2013

Active Measurement of Memory Resource Consumption

Hierarchical memory is a cornerstone of modern hardware design because it provides high memory performance and capacity at a low cost. However, the use of multiple levels of memory and complex cache management policies makes it very difficult to optimize the performance of applications running on hierarchical memories. As the number of compute cores per chip continues to rise faster than the total amount of available memory, applications will become increasingly starved for memory storage capacity and bandwidth, making the problem of performance optimization even more critical. We propose a new methodology for measuring and modeling the performance of hierarchical memories in terms on the application’s utilization of the key memory resources: capacity of a given memory level and bandwidth between two levels. This is done by actively interfering with the application’s use of these resources. The application’s sensitivity to reduced resource availability is measured by observing the effect of interference on application performance. The resulting resource-oriented model of performance both greatly simplifies application performance analysis and makes it possible to predict an application’s performance when running with various resource constraints. This is useful to predict performance for future memory-constrained architectures.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2018

Near-memory data reorganization engine

A memory subsystem package is provided that has processing logic for data reorganization within the memory subsystem package. The processing logic is adapted to reorganize data stored within the memory subsystem package. In some embodiments, the memory subsystem package includes memory units, a memory interconnect, and a data reorganization engine ("DRE"). The data reorganization engine includes a stream interconnect and DRE units including a control processor and a load-store unit. The control processor is adapted to execute instructions to control a data reorganization. The load-store unit is adapted to process data move commands received from the control processor via the stream interconnect for loading data from a load memory address of a memory unit and storing data to a store memory address of a memory unit.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2018

Smart memory buffers

An example method involves receiving, at a first memory node, data to be written at a memory location in the first memory node. The data is received from a device. At the first memory node, old data is read from the memory location, without sending the old data to the device. The data is written to the memory location. The data and the old data are sent from the first memory node to a second memory node to store parity information in the second memory node without the device determining the parity information. The parity information is based on the data stored in the first memory node.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2019

Memory address translation

A memory address translation apparatus comprises a translation data store to store one or more instances of translation data. Each instance provides address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and indicates a translation between a virtual memory address in the range of virtual memory addresses and a corresponding output memory address in an output address space. When a given virtual memory address to be translated lies outside the ranges of virtual memory addresses defined by any instances of the translation data stored by the translation data store, detector circuitry retrieves one or more further instances of the translation data and translation circuitry applies the translation defined by a detected instance of the translation data to the given virtual memory address.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2020

Smart memory buffers

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2025

Flexible and Effective Object Tiering for Heterogeneous Memory Systems

Computing platforms that package multiple types of memory, each with their own performance characteristics, are quickly becoming mainstream. To operate efficiently, heterogeneous memory architectures require new data management solutions that are able to match the needs of each application with an appropriate type of memory. As the primary generators of memory usage, applications create a great deal of information that can be useful for guiding memory management, but the community still lacks tools to collect, organize, and leverage this information effectively. To address this gap, this work introduces a novel software framework that collects and analyzes object-level information to guide memory tiering. The framework includes tools to monitor the capacity and usage of individual data objects, routines that aggregate and convert this information into tier recommendations for the host platform, and mechanisms to enforce these recommendations according to user-selected policies. Moreover, the developed tools and techniques are fully automatic, work on standard Linux systems, and do not require modification or recompilation of existing software. Using this framework, this study evaluates and compares the impact of a variety of design choices for memory tiering, including different policies for prioritizing objects for the fast memory tier as well as the frequency and timing of migration events. In conclusion, the results, collected on a modern Intel platform with conventional DDR4 SDRAM as well as Intel Optane NVRAM, show that guiding data tiering with object-level information can enable significant performance and efficiency benefits compared with standard hardware- and software-directed data-tiering strategies for a diverse set of memory-intensive workloads.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2021

Memory-Related Frontal Brainwaves Predict Transition to Mild Cognitive Impairment in Healthy Older Individuals Five Years Before Diagnosis

Background: Early prognosis of high-risk older adults for amnestic mild cognitive impairment (aMCI), using noninvasive and sensitive neuromarkers, is key for early prevention of Alzheimer’s disease. We have developed individualized measures in electrophysiological brain signals during working memory that distinguish patients with aMCI from age-matched cognitively intact older individuals. Objective: Here we test longitudinally the prognosis of the baseline neuromarkers for aMCI risk. We hypothesized that the older individuals diagnosed with incident aMCI already have aMCI-like brain signatures years before diagnosis. Methods: Electroencephalogram (EEG) and memory performance were recorded during a working memory task at baseline. The individualized baseline neuromarkers, annual cognitive status, and longitudinal changes in memory recall scores up to 10 years were analyzed. Results: Seven of the 19 cognitively normal older adults were diagnosed with incident aMCI for a median 5.2 years later. The seven converters’ frontal brainwaves were statistically identical to those patients with diagnosed aMCI (n = 14) at baseline. Importantly, the converters’ baseline memory-related brainwaves (reduced mean frontal responses to memory targets) were significantly different from those who remained normal. Furthermore, differentiation pattern of left frontal memory-related responses (targets versus nontargets) was associated with an increased risk hazard of aMCI (HR = 1.47, 95% CI 1.03, 2.08). Conclusion: The memory-related neuromarkers detect MCI-like brain signatures about five years before diagnosis. The individualized frontal neuromarkers index increased MCI risk at baseline. These noninvasive neuromarkers during our Bluegrass memory task have great potential to be used repeatedly for individualized prognosis of MCI risk and progression before clinical diagnosis.

59 BASIC BIOLOGICAL SCIENCES↗

DOE OSTI2023

Towards generic memory forensic framework for programmable logic controllers

A Programmable Logic Controller (PLC) is a microprocessor-based controller that is used to automate physical processes in critical infrastructure and various other industries and manufacturing sectors. Initially, PLCs were completely isolated from the Internet, and cyber security was not incorporated at the time of development. The introduction of industry 4.0 and the evolution of ICS systems to communicate over public IP addresses from the Internet enhanced productivity and efficiency, but Internet connectivity exposed the systems and their vulnerabilities, which led to an increase in cyber attacks. When a system is sabotaged/compromised, security analysts need to get to the root cause of the attack as quickly as possible to recover the system. To do so, memory forensic analysis is critical to provide a unique insight into the run-time memory activities and extract a reliable source of evidence. In this paper, we analyze the memory structure of the Schneider Electric Modicon M221 PLC. To build a memory profile, we reverse engineer the communication protocol and conduct differential analysis to gain knowledge about the structure of the memory and the low-level representation of control logic instructions. We then identify dynamic and static memory regions by modifying different project fields and conducting differential analysis, which allows us to identify boundaries of critical memory structures and extract important forensic artifacts that can be found in the memory. The Python implementation of the memory profile can help reduce the time and effort required for manual analysis in case of cyber incident or system failure.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2017

Benchmarking and Evaluating Unified Memory for OpenMP GPU Offloading

Here, the latest OpenMP standard offers automatic device offloading capabilities which facilitate GPU programming. Despite this, there remain many challenges. One of these is the unified memory feature introduced in recent GPUs. GPUs in current and future HPC systems have enhanced support for unified memory space. In such systems, CPU and GPU can access each other's memory transparently, that is, the data movement is managed automatically by the underlying system software and hardware. Memory over subscription is also possible in these systems. However, there is a significant lack of knowledge about how this mechanism will perform, and how programmers should use it. We have modified several benchmarks codes, in the Rodinia benchmark suite, to study the behavior of OpenMP accelerator extensions and have used them to explore the impact of unified memory in an OpenMP context. We moreover modified the open source LLVM compiler to allow OpenMP programs to exploit unified memory. The results of our evaluation reveal that, while the performance of unified memory is comparable with that of normal GPU offloading for benchmarks with little data reuse, it suffers from significant overhead when GPU memory is over subcribed for benchmarks with large amount of data reuse. Based on these results, we provide several guidelines for programmers to achieve better performance with unified memory.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2011

Performance and scalability evaluation of "Big Memory" on Blue Gene Linux.

We address memory performance issues observed in Blue Gene Linux and discuss the design and implementation of 'Big Memory' - an alternative, transparent memory space introduced to eliminate the memory performance issues. We evaluate the performance of Big Memory using custom memory benchmarks, NAS Parallel Benchmarks, and the Parallel Ocean Program, at a scale of up to 4,096 nodes. We find that Big Memory successfully resolves the performance issues normally encountered in Blue Gene Linux. For the ocean simulation program, we even find that Linux with Big Memory provides better scalability than does the lightweight compute node kernel designed solely for high-performance applications. Originally intended exclusively for compute node tasks, our new memory subsystem dramatically improves the performance of certain I/O node applications as well. We demonstrate this performance using the central processor of the LOw Frequency ARray radio telescope as an example.

59 BASIC BIOLOGICAL SCIENCES↗