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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 181 records · Page 10
All sourcesNASA NTRSDOE OSTI
NASA NTRS2009

Reconfigurable, Bi-Directional Flexfet Level Shifter for Low-Power, Rad-Hard Integration

Two prototype Reconfigurable, Bi-directional Flexfet Level Shifters (ReBiLS) have been developed, where one version is a stand-alone component designed to interface between external low voltage and high voltage, and the other version is an embedded integrated circuit (IC) for interface between internal low-voltage logic and external high-voltage components. Targeting stand-alone and embedded circuits separately allows optimization for these distinct applications. Both ReBiLS designs use the commercially available 180-nm Flex fet Independently Double-Gated (IDG) SOI CMOS (silicon on insulator, complementary metal oxide semiconductor) technology. Embedded ReBiLS circuits were integrated with a Reed-Solomon (RS) encoder using CMOS Ultra-Low-Power Radiation Tolerant (CULPRiT) double-gated digital logic circuits. The scope of the project includes: creation of a new high-voltage process, development of ReBiLS circuit designs, and adjustment of the designs to maximize performance through simulation, layout, and manufacture of prototypes. The primary technical objectives were to develop a high-voltage, thick oxide option for the 180-nm Flexfet process, and to develop a stand-alone ReBiLS IC with two 8-channel I/O busses, 1.8 2.5 I/O on the low-voltage pins, 5.0-V-tolerant input and 3.3-V output I/O on the high-voltage pins, and 100-MHz minimum operation with 10-pF external loads. Another objective was to develop an embedded, rad-hard ReBiLS I/O cell with 0.5-V low-voltage operation for interface with core logic, 5.0-V-tolerant input and 3.3-V output I/O pins, and 100-MHz minimum operation with 10- pF external loads. A third objective was to develop a 0.5- V Reed-Solomon Encoder with embedded ReBilS I/O: Transfer the existing CULPRiT RS encoder from a 0.35-micron bulk-CMOS process to the ASI 180-nm Flexfet, rad-hard SOI Process. 0.5-V low-voltage core logic. 5.0-V-tolerant input and 3.3-V output I/O pins. 100-MHz minimum operation with 10- pF external loads. The stand-alone ReBiLS chip will allow system designers to provide efficient bi-directional communication between components operating at different voltages. Embedding the ReBiLS cells into the proven Reed-Solomon encoder will demonstrate the ability to support new product development in a commercially viable, rad-hard, scalable 180-nm SOI CMOS process.

DeGregorio, Kelly↗
NASA NTRS1980

Study program to improve the open-circuit voltage of low resistivity single crystal silicon solar cells

The results of a 14 month program to improve the open circuit voltage of low resistivity silicon solar cells are described. The approach was based on ion implantation in 0.1- to 10.0-ohm-cm float-zone silicon. As a result of the contract effort, open circuit voltages as high as 645 mV (AMO 25 C) were attained by high dose phosphorus implantation followed by furnace annealing and simultaneous SiO2 growth. One key element was to investigate the effects of bandgap narrowing caused by high doping concentrations in the junction layer. Considerable effort was applied to optimization of implant parameters, selection of furnace annealing techniques, and utilization of pulsed electron beam annealing to minimize thermal process-induced defects in the completed solar cells.

Minnucci, J. A.↗
DOE OSTI2020

Investigation of Dynamic Temperature-Sensitive Electrical Parameters for Medium-Voltage Low-Current Silicon Carbide and Silicon Devices

This paper presents five dynamic temperature-sensitive electrical parameters (TSEPs) for the medium-voltage silicon carbide (SiC) and silicon (Si) devices. The theoretical temperature dependence of these parameters is analyzed. A test platform that enables to implement the temperature relevant dynamic characterization is developed. The tested TSEPs are summarized in terms of their relationship with junction temperature, drain/collector current, DC voltage, and external gate resistance. The comparison between the 3 kV 12 A Si IGBT and 3.3 kV 5 A SiC MOSFET with the identical TO-263 package is conducted. The results verify that the turn-off drain-source voltage switching rate achieves better thermal sensitivity for medium-voltage low-current SiC MOSFETs compared with Si IGBTs. Both the turn-on and turn-off delay time exhibit better thermal linearity for the two devices. The turn-off delay time further achieves five times better thermal sensitivity than the turn-on delay time for investigated medium-voltage SiC MOSFETs.

Ni, Ze↗
DOE OSTI2022

Supervised Learning for Distribution Secondary Systems Modeling: Improving Solar Interconnection Processes

The current interconnection process and hosting capacity analysis for distributed energy resources (DERs), such as photovoltaics (PV) and battery energy storage systems, are based on analyzing grid network constraints (voltage and thermal) using only medium-voltage distribution network models. This is because most utilities do not have secondary low-voltage system models that connect service transformers and residential customers. This is important because in many cases the main impact of interconnecting DERs could occur on the low-voltage distribution systems. This paper proposes a supervised learning method to approximate local secondary models to improve the interconnection process. The proposed supervised learning method includes a decision tree model that predicts the secondary topology and a logistic regression model that predicts conductor types. The case studies demonstrate the benefits of including secondary low-voltage circuits in the interconnection process. We report the proposed modeling methodology is readily scalable and thus can reduce the cost and effort of PV interconnection for the industry and stakeholders.

14 SOLAR ENERGY↗
NASA NTRS2012

High-Voltage, Low-Power BNC Feedthrough Terminator

This innovation is a high-voltage, lowpower BNC (Bayonet Neill-Concelman) feedthrough that enables the user to terminate an instrumentation cable properly while connected to a high voltage, without the use of a voltage divider. This feedthrough is low power, which will not load the source, and will properly terminate the instrumentation cable to the instrumentation, even if the cable impedance is not constant. The Space Shuttle Program had a requirement to measure voltage transients on the orbiter bus through the Ground Lightning Measurement System (GLMS). This measurement has a bandwidth requirement of 1 MHz. The GLMS voltage measurement is connected to the orbiter through a DC panel. The DC panel is connected to the bus through a nonuniform cable that is approximately 75 ft (approximately equal to 23 m) long. A 15-ft (approximately equal to 5-m), 50-ohm triaxial cable is connected between the DC panel and the digitizer. Based on calculations and simulations, cable resonances and reflections due to mismatched impedances of the cable connecting the orbiter bus and the digitizer causes the output not to reflect accurately what is on the bus. A voltage divider at the DC panel, and terminating the 50-ohm cable properly, would eliminate this issue. Due to implementation issues, an alternative design was needed to terminate the cable properly without the use of a voltage divider. Analysis shows how the cable resonances and reflections due to the mismatched impedances of the cable connecting the orbiter bus and the digitizer causes the output not to reflect accurately what is on the bus. After simulating a dampening circuit located at the digitizer, simulations were performed to show how the cable resonances were dampened and the accuracy was improved significantly. Test cables built to verify simulations were accurate. Since the dampening circuit is low power, it can be packaged in a BNC feedthrough.

Bearden, Douglas↗
NASA NTRS2006

Effects of Displacement Damage on the Time-Resolved Gain and Bandwidth of a Low Breakdown Voltage Si Avalanche Photodiode

Effects of displacement damage and ionization damage induced by gamma irradiation on the dark current and impulse response of a high-bandwidth low breakdown voltage Si Avalanche Photodiode has been investigated using picosecond laser microscopy. At doses as high as 10Mrad (Si) minimal alteration in the impulse response and bandwidth were observed. However, dark current measurements also performed with and without biased irradiation exhibit anomalously large damage factors for applied biases close to breakdown. The absence of any degradation in the impulse response is discussed as are possible mechanisms for higher dark current damage factors observed for biased irradiation.

bandwidth↗
NASA NTRS1983

High voltage battery cell scanner development

Battery cell voltage scanners have been previously used in low voltage spacecraft applications. In connection with future missions involving an employment of high-power high voltage power subsystems and/or autonomous power subsystem management for unattended operation, it will be necessary to utilize battery cell voltage scanners to provide battery cell voltage information for early detection of impending battery cell degradation/failures. In preparation for such missions, a novel battery cell voltage scanner design has been developed. The novel design makes use of low voltage circuit modules which can be applied to high voltage batteries in a building block fashion. A description is presented of the design concept and test results of the high voltage battery cell scanner, and its operation with an autonomously managed power subsystem is discussed.

Lepisto, J. W.↗
NASA NTRS1988

Arc lamp power supply using a voltage multiplier

A power supply is provided for an arc discharge lamp which includes a relatively low voltage high current power supply section and a high voltage starter circuit. The low voltage section includes a transformer, rectifier, variable resistor and a bank of capacitors, while the starter circuit comprises several diodes and capacitors connected as a Cockcroft-Walton multiplier. The starting circuit is effectively bypassed when the lamp arc is established and serves to automatically provide a high starting voltage to re-strike the lamp arc if the arc is extinguished by a power interruption.

Leighty, Bradley D.↗
DOE OSTI2022

Nondestructive Evaluation (NDE) of Cable Anomalies using Frequency Domain Reflectometry (FDR) and Spread Spectrum Time Domain Reflectometry (SSTDR)

This report presents a comparative assessment of the performance of frequency domain reflectometry (FDR) and spread spectrum time domain reflectometry (SSTDR) in detecting a wide range of electrical cable anomalies. All tests and results reported herein were performed at the PNNL Accelerated and Real-Time Environmental Nodal Assessment (ARENA) cable and motor test bed. The primary objective of this work was to evaluate the effectiveness of SSTDR, a fledgling cable monitoring technique that shows promise for application in online monitoring of energized cable systems, against FDR, an offline technique widely employed in the nuclear power plant (NPP) industry. FDR tests are becoming more widely used in nuclear power plant cable aging management and test programs – particularly for low voltage cables. FDR capabilities for these kinds of tests have been reported by PNNL and others. The FDR test is performed on de-energized cables by connecting the FDR instrument to two of the cable conductors, or one conductor and the shield. A broad band low voltage (< 5 V) chirp is introduced in the cable, and any reflected response is captured in the frequency domain. The captured reflection is then processed by performing an inverse Fourier transform to a time domain response which can then be converted to a distance response based on the cable velocity of propagation (VoP). SSTDR measurements are functionally similar to FDR measurements in that a broad-band voltage signal composed of a square or sine wave modulated pseudo-random sequence of chips (< 5 volts), is injected onto one of the cable conductors. The injected signal will experience partial energy reflection and transmission at each impedance discontinuity along the transmission line. Any reflected response is detected by computing a cross-correlation between the reflected signals and a delayed copy of the incident SSTDR signal. the time delay for the reflected signal to experience the best matched correlation with the incident signal, indicates the travel time for the signal to reach a change in impedance. By knowing this time delay and velocity of propagation (VoP) of the signal, one can compute the physical distance. A big advantage that SSTDR measurements have over other methods is the ability to be connected to energized or live wires (currently up to 1kV) thereby enabling online monitoring of cables. SSTDR has been used successfully in several applications, e.g., aircraft, rail, and photovoltaic systems. In this work FDR and SSTDR cable assessment techniques were used to characterize a variety of cable anomalies and faults including: (1) Presence or absence of a motor; (2) Ground faults and short circuit faults; (3) Moist environments and water ingress faults; (4) Accelerated thermal aging. Both shielded and non-shielded cables were evaluated in this report. Offline measurements were made using FDR and online measurements were made by SSTDR for a range of test scenarios. Based on the results across all cable anomalies evaluated in this study, FDR displayed high sensitivity towards cable condition assessment, while SSTDR showed promise for future application in monitoring NPP cable systems. However, further developments are suggested to improve the resolution and sensitivity of SSTDR towards faults and anomalies in low voltage cables.rt presents a comparative

42 ENGINEERING↗
DOE OSTI2022

1 kV, 10-kW SiC-Based Quadruple Active Bridge DCX Stage in a DC to Three-Phase AC Module for Medium-Voltage Grid Integration

Interfacing low voltage dc to medium voltage three-phase ac grid is often based on series-stackable modular converter architectures. To minimize energy storage requirements, it is advantageous to employ a quadruple active bridge (QAB) stage operating as a "dc transformer" in each stackable module. The QAB stage offers three isolated dc link voltages, which then allow for flexible stacking of three single-phase dc-to-ac inverter stages. Each of the module phases processes a pulsating power having a component at twice the line frequency. This presents a challenge in maintaining zero voltage switching (ZVS) on the secondary sides of the QAB during low-power portions of the line cycle. This article is focused on the design of the QAB stage. A detailed analysis of ZVS switching waveforms is presented, including effects of nonlinear device capacitances. It is shown how ZVS can be achieved at all times using a relatively small circulating current provided by the magnetizing inductance of the high-frequency transformer. Analytical expressions are given for the optimal values of the magnetizing inductance and the dead times of the QAB primary and secondary bridges. This approach is verified by experimental results on a 1 kV, 10-kW SiC-based prototype, demonstrating a relatively flat efficiency curve with a peak efficiency of 97.1% at 75% load.

24 POWER TRANSMISSION AND DISTRIBUTION↗
DOE OSTI2025

Analysis of Niobium Electropolishing Using a Generalized Distribution of Relaxation Times Method

Using electrochemical impedance spectroscopy, we have devised a method of sensing the microscopic surface conditions on the surface of niobium as it is undergoing an electrochemical polishing (EP) treatment. The method uses electrochemical impedance spectroscopy (EIS) to gather information on the surface state of the electrode without disrupting the polishing reaction. The EIS data is analyzed using a so-called distribution of relaxation times (DRT) method. Using DRT, the EIS data can be deconvolved into discrete relaxation time peaks without any a priori knowledge of the electrode dynamics. By analyzing the relaxation time peaks, we are able to distinguish two distinct modes of the EP reaction. As the polishing voltage is increased, the electrode transitions from the low voltage EP mode, characterized by a single relaxation time peaks, to the high voltage EP mode, characterized by two relaxation time peaks. We theorize that this second peak is caused by the formation of an oxide layer on the electrode. We also find that this oxide induced peak transitions from to a negative relaxation time, which is indicative of a blocking electrode process. By analyzing EPed samples, we show that samples polished in the low voltage mode have significantly higher surface roughness due to grain etching and faceting. We find that the surface roughness of the samples only improves when the oxide film peak is present and in the negative relaxation time region. This shows that EIS combined with DRT analysis can be used to predict etching on EPed Nb. This method can also be performed before or during the EP, which could allow for adjustment of polishing parameters to guarantee a smooth cavity surface finish.

43 PARTICLE ACCELERATORS↗
NASA NTRS1978

Stable low noise voltage source

Hum and noise on power sources can have a significant effect on system noise. Filtering to achieve low hum and noise is accomplished at low current levels. The diode regulator circuit is described which is ideal for this type of filtering. Hum and noise rejection is achieved with good output voltage stability in a small, low-cost, reliable circuit.

Lutes, G. F.↗