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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 181 records · Page 10
All sourcesNASA NTRSDOE OSTI
NASA NTRS1992

InGaAs/InGaAsP/InP strained-layer quantum well lasers at about 2 microns

The first successful operation of InGaAs strained layer quantum well (Sl-QW) injection lasers at about 2 microns is reported. The threshold current density and the external differential quantum efficiency of 5 microns wide and 800 microns long ridge waveguide lasers were 2.5 kA/sq cm and 6 percent, respectively. The devices had a reverse leakage current of less than 20 micro-A at -1 V indicating epitaxial layers with low defect density.

Forouhar, S.↗
DOE OSTI2021

A Custom Low-Noise Silicon Photodiode Detector Designed for Use With X-Ray Capillary Optics

We present the first results of a custom low-noise silicon photodiode detector designed for use with X-ray capillary optics. This system is intended to perform as a smaller, lighter, and low-powered alternative to currently existing X-ray telescope technologies. The detector has an active area with a diameter of 100 μm, and its small size leads to a low capacitance of well under 1 pF and a leakage current of 1 pA or less at the depletion voltage. We tested the detector with both a discrete preamp and an ultralow-noise front-end application-specific integrated circuit (ASIC). The front-end ASIC, developed at Brookhaven National Laboratory, was designed for low-capacitance detectors but had not been previously tested with a detector. Here, we discuss the detector design, the experimental setup, and the resulting detector performance. Using radioactive laboratory sources, we measure a full-width at half-maximum (FWHM) of 211 ± 8 eV at 5.9 keV with the ASIC and are able to set the threshold as low as 0.6 keV.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Investigation of Interlayer Dielectric in BaTiO 3 /III–Nitride Transistors

In this paper, the impact of varying the thickness of the Al 2 O 3 interlayer dielectric on the electrical characteristics of BaTiO 3 /III-nitride transistors is investigated. In the findings, it is revealed that a minimum thickness of 8 nm for the Al 2 O 3 layer is crucial to maintain high device performance and protect against sputtering-induced damage during BaTiO 3 deposition. The fabricated BaTiO 3 /Al 2 O 3 /AlGaN/GaN high electron mobility transistors exhibit exceptional electrical properties, including a maximum current density of 700 mA mm –1 , an on-resistance of 5 Ω mm, an I ON /I OFF ratio of 10 7 , a subthreshold slope of 119 mV dec –1 , and significantly reduced gate leakage current. The devices with the optimal 8 nm Al 2 O 3 thickness demonstrates excellent agreement between theoretical and experimental values for effective mobility, achieving a value of 1188 cm 2 V –1 ·s at a 2D electron gas density of 10 13 cm –2 . Furthermore, in the study, it is confirmed that increasing the Al 2 O 3 thickness also improves the quality of interface charge density, as evidenced by the results obtained from capacitance–voltage measurements. In these findings, the critical role of controlling the Al 2 O 3 thickness in optimizing the electrical characteristics and overall performance of BaTiO 3 /III-nitride transistors are highlighted.

42 ENGINEERING↗
DOE OSTI2026

A Unidirectional Two-Compartment Neuron Circuit with On-chip STDP learning

Most neuromorphic chips implement the single-compartment point neuron model where synapse circuits connect directly to a leaky integrate and fire (LIF) soma circuit. However, when using a biologically plausible soma circuit (e.g., Hodgkin-Huxley neuron model), an interface circuitry, such as a current conveyor circuit, is needed to transmit synaptic current to the soma circuit. This is especially true for ultra-low power neuron circuits, where membrane capacitance is on the order of 20 fF. This need for an interface circuit arises because the parasitic capacitance and leakage current caused by fabrication mismatch and second-order effects of the output transistors in the synapse circuits can disturb the spiking dynamics of the soma circuit if connected without an interface. Using an interface circuit to isolate the soma’s membrane capacitor from synapses resolves this issue. We propose to use a unidirectional resistor (a transconductance circuit) to connect the synapse and soma circuits instead of conventional current conveyor circuits. Using a biologically plausible spike pattern detection model, we show that the on-chip spike-timing-dependent plasticity (STDP) learning performance of the proposed unidirectional two-compartment neuron circuit is similar to a single-compartment circuit (with a current conveyor as an interface) and additionally, it is more power-efficient and biologically plausible. The chip is fabricated in the Taiwan Semiconductor Manufacturing Company (TSMC) 250 nm technology node and comprises a single neuron circuit.

Gautam, Ashish [ORNL]↗
DOE OSTI2020

Direct metal contacts printing on 4H-SiC for alpha detectors and inhomogeneous Schottky barriers

Electrical characterization of several 4H-SiC Schottky diodes with Aerosol-Jet printed gold (Au), silver (Ag), and platinum (Pt) contacts was performed using forward and reverse current–voltage (IV) measurements. From these measurements, device parameters such as Schottky barrier height and ideality factor were determined; however, many of the devices exhibited nonideal behavior and inferior performance characterized by ideality factors significantly greater than one, disproportionate low voltage leakage current and low barrier heights. Forward current–voltage (FIV) characteristics were fitted to an inhomogeneous barrier height theory to explain the abnormal behavior exhibited by the printed devices. Here, transmission electron microscopy (TEM) of the device cross-sections was performed to investigate the printed metal and semiconductor epitaxial layer interface, which revealed the imperfections in the metal–semiconductor contact. Despite these irregularities, alpha radiation detection capability of these devices was still achieved with an energy resolution of 1.89% at 5.486 MeV, and the best achievable resolution at 0.51% with no energy degradation of 5.486 MeV.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2021

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MISHEMTs) using plasma deposited BN as gate dielectric

AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MISHEMTs) were fabricated on Si substrates with a 10 nm boron nitride (BN) layer as a gate dielectric deposited by electron cyclotron resonance microwave plasma chemical vapor deposition. The material characterization of the BN/GaN interface was investigated by X-ray photoelectric spectroscopy (XPS) and UV photoelectron spectroscopy. The BN bandgap from the B1s XPS energy loss is ~5 eV consistent with sp2 bonding. The MISHEMTs exhibit a low off-state current of 1 × 10 –8 mA/mm, a high on/off current ratio of 10 9 , a threshold voltage of –2.76 V, a maximum transconductance of 32 mS/mm at a gate voltage of –2.1 V and a drain voltage of 1 V, a subthreshold swing of 69.1 mV/dec, and an on-resistance of 12.75 Ω·mm. The interface state density (D it ) is estimated to be less than 8.49 × 10 11 cm –2 eV –1 . Gate leakage current mechanisms were investigated by temperature-dependent current–voltage measurements from 300 K to 500 K. The maximum breakdown electric field is no less than 8.4 MV/cm. Poole–Frenkel emission and Fowler–Nordheim tunneling are indicated as the dominant mechanisms of the gate leakage through the BN gate dielectric at low and high electric fields, respectively.

36 MATERIALS SCIENCE↗
NASA NTRS1992

Room-temperature operation of MOCVD-grown GaInAs/InP strained-layer multiquantum well lasers in 1.8 micron range

The first successful room-temperature pulsed operation is reported of InGaAs strained layer multiquantum well injection lasers grown by MOVPE on InP substrates in the 1.8 micron range. The threshold current density and the external differential quantum efficiency of the 10 micron wide ridge waveguide lasers were 2.5 kA/sq cm (cavity length = 1 mm) and 5 percent (cavity length = 400 microns), respectively. Broad-area lasers, 100 microns wide and 1 mm long, had a reverse leakage current of less than 10 microamps at -1 V indicating high quality of the epitaxial layers.

Forouhar, S.↗
DOE OSTI2024

Interband cascade light-emitting diodes grown on silicon substrates using GaSb buffer layer

Interband cascade light-emitting diodes (ICLEDs) offer attractive advantages for infrared applications, which would greatly expand if high-quality growth on silicon substrates could be achieved. Here, this work describes the formation of threading dislocations in ICLEDs grown monolithically on GaSb-on-Silicon wafers. The epitaxial growth is done in two stages: the GaSb-on-Silicon buffer is grown first, followed by the ICLED growth. The buffer growth involves the nucleation of a 10-nm-thick AlSb buffer layer on the silicon surface, followed by the GaSb growth. The AlSb nucleation layer promotes the formation of 90° and 60° interfacial misfit dislocations, resulting in a highly planar morphology for subsequent GaSb growth that is almost 100% relaxed. The resulting GaSb buffer for growth of the ICLED has a threading dislocation density of ~10 7 /cm 2 after ~3 μm of growth. The fabricated LEDs showed variations in device performance, with some devices demonstrating comparable light–current–voltage curves to those for devices grown on GaSb substrates, while other devices showed somewhat reduced relative performance. Cross-sectional transmission electron microscopy observations of the inferior diodes indicated that the multiplication of threading dislocations in the active region had most likely caused the increased leakage current and lower output power. Enhanced defect filter layers on the GaSb/Si substrates should provide more consistent diode performance and a viable future growth approach for antimonide-based ICLEDs and other infrared devices.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS1998

Breakdown Degradation Associated with Elementary Screw Dislocations in 4H-SiC P(+)N Junction Rectifiers

It is well-known that SiC wafer quality deficiencies are delaying the realization of outstandingly superior 4H-SiC power electronics. While efforts to date have centered on eradicating micropipes (i.e., hollow core super-screw dislocations with Burgers vector greater than 2c), 4H-SiC wafers and epilayers also contain elementary screw dislocations (i.e., Burgers vector = lc with no hollow core) in densities on the order of thousands per sq cm, nearly 100-fold micropipe densities. This paper describes an initial study into the impact of elementary screw dislocations on the reverse-bias current-voltage (I-V) characteristics of 4H-SiC p(+)n diodes. First, Synchrotron White Beam X-ray Topography (SWBXT) was employed to map the exact locations of elementary screw dislocations within small-area 4H-SiC p(+)n mesa diodes. Then the high-field reverse leakage and breakdown properties of these diodes were subsequently characterized on a probing station outfitted with a dark box and video camera. Most devices without screw dislocations exhibited excellent characteristics, with no detectable leakage current prior to breakdown, a sharp breakdown I-V knee, and no visible concentration of breakdown current. In contrast devices that contained at least one elementary screw dislocation exhibited a 5% to 35% reduction in breakdown voltage, a softer breakdown I-V knee, and visible microplasmas in which highly localized breakdown current was concentrated. The locations of observed breakdown microplasmas corresponded exactly to the locations of elementary screw dislocations identified by SWBXT mapping. While not as detrimental to SiC device performance as micropipes, the undesirable breakdown characteristics of elementary screw dislocations could nevertheless adversely affect the performance and reliability of 4H-SiC power devices.

Neudeck, P. G.↗
NASA NTRS1987

Advanced Components for Spaceborne Infrared Astronomy

Basic improvements in the technology of low noise read-out systems for low background detectors were demonstrated. Using discrete JFET integrating amplifiers at their optimum temperature of 55 K, read noise less than 7.5 electrons in 128 seconds of integration was obtained. Two models of single channel integrators are now available, the JF-77 for use between 50 and 80 K and the JF-4 for lower temperatures. A 1 x 15 linear array of complete integrators on a single integrated circuit was developed and will be made available in the near future. The successful operation of a superconducting stepper motor was demonstrated. The motor shows a three fold increase in torque over conventional motors operating at room temperature. The success of the motor stems from the use of superconducting coils in conjunction with developments in bearings for cryogenic use, rare-earth rotors, and motor cooling techniques. The current state of development will allow the rapid development of motors optimized for specific applications. An electronic switch capable of resetting cooled JFET integrating amplifiers was developed. The JFET integrating amplifiers that use this switch have demonstrated read noise of less than 10 electrons. The JFET reset device exhibits an extremely high open impedance and low leakage current. Capacitance is sufficiently low so as not to impair amplifier sensitivity. The effects of transient switching charges are minimized by a compensation technique and variable transient current problems inherent to devices of this type are overcome by external circuity.

Davidson, Arnold W.↗
NASA NTRS1998

Numerical Examination of Silicon Avalanche Photodiodes Operated in Charge Storage Mode

The behavior of silicon-based avalanche photodiodes (APD's) operated in the charge storage mode is examined. In the charge storage mode, the diodes are periodically biased to a sub-breakdown voltage and then open-circuited. During this integration period, photo-excited and thermally generated carriers are accumulated within the structure. The dynamics of this accumulation and its effects upon the avalanching of the diode warrants a detailed, fully numerical analysis. The salient features of this investigation include device sensitivity to the input photo-current including the self-quenching effect of the diode and its limitations in sensing low light levels, the dependence of the response on the bulk lifetime and hence on the generation current within the device, the initial gain, transient response, dependence of the device uniformity upon performance, and the quantity of storable charge within the device. To achieve these tasks our device simulator, STEBS-2D, was utilized. A modified current-controlled boundary condition is employed which allows for the simulation of the isolated diode after the initial reset bias has been applied. With this boundary condition, it is possible to establish a steady-state voltage on the ohmic contact and then effectively remove the device from the external circuit while still including effects from surface recombination, trapped surface charge, and leakage current from the read-out electronics.

Parks, Joseph W., Jr.↗
DOE OSTI2024

Highly Efficient Room‐Temperature Spin‐Orbit‐Torque Switching in a Van der Waals Heterostructure of Topological Insulator and Ferromagnet

Abstract All‐Van der Waals (vdW)‐material‐based heterostructures with atomically sharp interfaces offer a versatile platform for high‐performing spintronic functionalities at room temperature. One of the key components is vdW topological insulators (TIs), which can produce a strong spin‐orbit‐torque (SOT) through the spin‐momentum locking of their topological surface state (TSS). However, the relatively low conductance of the TSS introduces a current leakage problem through the bulk states of the TI or the adjacent ferromagnetic metal layers, reducing the interfacial charge‐to‐spin conversion efficiency ( q ICS ). Here, a vdW heterostructure is used consisting of atomically‐thin layers of a bulk‐insulating TI Sn‐doped Bi 1.1 Sb 0.9 Te 2 S 1 and a room‐temperature ferromagnet Fe 3 GaTe 2, to enhance the relative current ratio on the TSS up to ≈20%. The resulting q ICS reaches ≈1.65 nm −1 and the critical current density J c ≈0.9 × 10 6 Acm −2 at 300 K, surpassing the performance of TI‐based and heavy‐metal‐based SOT devices. These findings demonstrate that an all‐vdW heterostructure with thickness optimization offers a promising platform for efficient current‐controlled magnetization switching at room temperature.

2D ferromagnet↗
DOE OSTI2022

Probing crystallographic orientation-specific carrier lifetimes in epitaxial Ge/AlAs and InGaAs/InP heterostructures

Current silicon (Si) fin transistors rely on (100) and (110) crystallographically oriented surfaces, and the proposed alternate channel transistor technology comprises materials with higher mobility than Si. Crystallographically oriented epitaxial germanium (Ge) and indium–gallium arsenide (InGaAs) have the potential to replace Si in ultra-low power transistor applications. The higher carrier lifetime is an indication of superior material quality, which relates to the leakage current of a fin transistor. To gain insights into the carrier recombination dynamics in these crystallographically oriented epitaxial Ge and InGaAs layers, the contactless microwave photoconductive decay (μ-PCD) technique at an excitation wavelength of 1500 nm was employed to probe the orientation-specific carrier lifetimes. Highly effective carrier lifetimes >200 ns for (100)Ge/AlAs and (110)Ge/AlAs, and ~80 ns for (111)Ge/AlAs heterostructures, were extracted at room temperature. The measured carrier lifetime has a strong dependence on the surface orientation, which could be related to orientation-specific bulk trap states present within the bandgap of Ge. The (111)Ge orientation has 3 times lower carrier lifetime compared to the (100)Ge and (110)Ge surface orientations. On the other hand, the carrier lifetimes of 125 μs and 10 ns were determined from (100)InGaAs/InP and (110)InGaAs/InP heterostructures, respectively. The reduction in carrier lifetimes in both (111)Ge and (110)InGaAs was due to high electrical conductivity or higher bulk trap states present within the bandgap as well as the facet-dependent growth of the (110)InGaAs layer on InP. A surface passivating layer is indispensable for these orientation-specific epitaxial layers to improve the carrier lifetime. Therefore, the higher carrier lifetimes from technologically interesting (100)Ge and (110)Ge surfaces would offer a path for the development of Ge-based ultra-low power electronics, and optoelectronic devices based on the (100)InGaAs layer.

36 MATERIALS SCIENCE↗
NASA NTRS2014

Evaluation of Polymer Hermetically Sealed Tantalum Capacitors

Polymer cathode tantalum capacitors have lower ESR (equivalent series resistance) compared to other types of tantalum capacitors and for this reason have gained popularity in the electronics design community. Their use allows improved performance of power supply systems along with substantial reduction of size and weight of the components used. However, these parts have poor thermal stability and can degrade in humid environments. Polymer hermetically sealed (PHS) capacitors avoid problems related to environmental degradation of molded case parts and can potentially replace current wet and solid hermetically sealed capacitors. In this work, PHS capacitors manufactured per DLA LAM DWG#13030 are evaluated for space applications. Several lots of capacitors manufactured over period from 2010 to 2014 were tested for the consistency of performance, electrical and thermal characteristics, highly accelerated life testing, and robustness under reverse bias and random vibration conditions. Special attention was given to analysis of leakage currents and the effect of long-term high temperature storage on capacitors in as is condition and after hermeticity loss. The results show that PHS capacitors might be especially effective for low-temperature applications or for system requiring a cold start-up. Additional screening and qualification testing have been recommended to assure the necessary quality of capacitors for space projects.

ferrite beads↗
DOE OSTI2025

The detrimental ratio ( ρ ): A critical metric complementing coulombic loss for long calendar-life silicon-based lithium-ion batteries

Silicon (Si) is a promising high-capacity anode in lithium-ion batteries but suffers from chronic chemical degradation and capacity fading during calendar aging, greatly hindering its automobile applications. Electrolyte engineering currently relies on conventional evaluation criteria of reducing coulombic consumption, which implicitly presume its equivalence to irreversible capacity loss and complicates battery development. Here, we introduce the detrimental ratio p to quantify the fraction of parasitic species that permanently degrades active material. This metric is independent and crucially complements total coulombic consumption for accurate performance evaluation. We systematically investigate multiple electrolyte formulations using high-precision leakage current measurements, open-circuit-voltage experiments, and post-mortem characterizations. Although some electrolytes exhibit similarly low coulombic consumption, they diverge significantly incapacity retention and p. Especially, dimethyl-carbonate-based localized-high concentration electrolyte can synergically achieve low coulombic consumption and detrimental ratio p during calendar aging, owing to its chemically inert and structurally resilient solidelectrolyte interface with minimal isolated Si material. By contrast, increasing fluoroethylene carbonate (FEC) additive content suppresses electrolyte breakdown but suffers aggravated chemical degradation of more LixSi isolation for irreversible capacity loss with arising p. This study critically reveals that the chemistry-characteristic detrimental ratio p establishes physically informed performance evaluation to pave the way for accelerating battery development.

Calendar aging↗
DOE OSTI2023

1.2-kV Vertical GaN PIN Rectifier With Ion-Implanted Floating Guard Rings

Here, this work reports on the fabrication and properties of a homojunction gallium nitride (GaN) p-i-n (PIN) rectifier fabricated on a free-standing GaN substrate. Uniform device performance is achieved with breakdown voltage (BV) >1.2 kV and low ON-resistance × area ( R ON A ). The statistics of the BV measurements show 58.5% of devices achieve BV >1.3 kV, and 71.1% of devices achieve BV >1.2 kV, as attributed to high quality and control in both epitaxial growth and device process. At room temperature, R ON A is 0.23 mΩ∙ cm 2 at a current density ( J ) of 6.9 kA/cm2. The corresponding Baliga’s figure of merit is >5.97 GW/cm 2 . Temperature-dependent reverse I – V measurements were performed and show a positive temperature coefficient of 0.42 V/K, indicating the avalanche capability of reverse breakdown. Further analysis with the Poole-Frenkel model on the temperature-dependent measurement suggested that a trap-assisted tunneling process contributed to the reverse leakage current. Floating guard rings (FGRs) formed by nitrogen implantation serve as an effective edge termination technique in these GaN PIN rectifiers, resulting in uniform performance in both forward and reverse bias.

42 ENGINEERING↗
DOE OSTI2024

Double-Side Cooled 1.2kV, 300A SiC MOSFET Phase-leg Modules for 200 kW, > 100 kW/L Traction Inverters

The packaging of a double-side cooled 1.2 kV, 149 A SiC phase-leg modules has been reported in recent years for making 100 kW, 100 kW/L traction inverters. Each phase-leg module consists of two SiC MOSFETs, one per switch position. Six of the phase-leg modules are assembled into a segmented inverter configuration to meet the power and power density requirement. In this work, the layout of the phase-leg module was redesigned to include four of the SiC MOSFETs, two per switch position, with the aim of doubling the power to 200 kW and increasing the power density beyond 100 kW/L, but with only a 10.25% footprint increase. Key features of the packaging technology developed in the previous work were implemented in the current work, which include silver sintering for chip bonding and porous silver inter-posts for bonding device source pads to substrate. Parasitic extraction simulation showed that the four-chip module has a low parasitic inductance of 4.7 nH, like the two-chip module. Static characterization of the four-chip prototypes showed a low average on-resistance of 9 mΩ and a low average leakage current of 5 nA at Vds of 1.2 kV.

Zhang, Zichen↗
NASA NTRS1991

PASP, a high voltage array/plasma interaction experiment

The author discusses the photovoltaic array space power (PASP) experiment, which is designed to obtain data on the interaction between high-voltage photovoltaic arrays and the polar, low-earth plasma environment. Up to six small test arrays (three each of planar and concentrator designs) can be voltage biased over a range of +/- 500 V. During the bias voltage sequence, the array current leakage is measured and array arc events are monitored. If any arcing occurs the arc characteristics will be measured by a transient pulse monitor. An emitter is included to allow voltage bias to be applied to a plasma-charged or uncharged spacecraft. Similarly, the frames of the concentrator arrays can be left floating or can be tied to the negative array terminal. An environmental data scan is made before each bias voltage sequence. This scan collects information on the plasma, array-current-versus-voltage curves, and neutral particle partial pressure. The requirement for high voltages created problems which were met by circuit isolation and logical fault protection.

Burger, Dale R.↗