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Permanent and transient effects are discussed that are induced in linear integrated circuits by space radiation. Recent developments include enhanced damage at low dose rate, increased damage from protons due to displacement effects, and transients in digital comparators that can cause circuit malfunctions.
A significant reduction in total dose damage is observed when bipolar integrated circuits are irradiated at low temperature. This can be partially explained by the Onsager theory of recombination, which predicts a strong temperature dependence for charge yield under low-field conditions. Reduced damage occurs for biased as well as unbiased devices because the weak fringing field in thick bipolar oxides only affects charge yield near the Si/SiO2 interface, a relatively small fraction of the total oxide thickness. Lowering the temperature of bipolar ICs - either continuously, or for time periods when they are exposed to high radiation levels - provides an additional degree of freedom to improve total dose performance of bipolar circuits, particularly in space applications.
At HiTEC2018, NASA Glenn Research Center reported the first demonstration of yearlong 500°C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021submissionupdateson-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11and near 3000 transistors/chip for Gen. 12 aremade possibleby reductions in minimum layout feature sizes (including resistorwidth shrinkage from 6 μm to 2μm) coupled with enlarged die size (from 3x3 mm to 5x5mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM)and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequentGen. 12 fabrication runcurrentlyin progress.
Single-event upsets (SEU's) propagate to adjacent cells in integrated memory circuits. Findings of experiments in lateral transport of electrical-charge carriers from ion tracks in 256K dynamic randon-access memories (DRAM's). As dimensions of integrated circuits decrease, vulnerability to SEU's increases. Understanding gained enables design of less vulnerable circuits.
At HiTEC 2018, NASA Glenn Research Center reported the first demonstration of yearlong 500 °C operation of ceramic-packaged “Generation 10” ~200-transistor integrated circuits (ICs) based on two-level interconnect silicon carbide (4H-SiC) junction field effect transistors and resistors (JFET-R). This HiTEC 2021 submission updates on-going efforts at NASA Glenn spanning two subsequent prototype IC generations “11 and 12” to increase both complexity and durability of these ICs. Increased chip complexities of around 1000 transistors/chip for Gen. 11 and near 3000 transistors/chip for Gen. 12 are made possible by reductions in minimum layout feature sizes (including resistor width shrinkage from 6 µm to 2 µm) coupled with enlarged die size (from 3 x 3 mm to 5 x 5 mm). Gen. 11 ICs electrically tested to date include an 8-bit delta-sigma analog to digital converter (ADC) as well as upscaled random access memory (RAM) and nearly 1 kbit read only memory (ROM). However, Gen. 11 prototype ICs exhibited significantly lower yield and durability than Gen. 10 ICs. Development of revised processing is being investigated towards mitigating these issues in subsequent Gen. 12 fabrication run currently in progress.
Design criteria for solid state electronic, high speed iterative differential analyzer using integrated circuits
Proton irradiation effects in MOS and junction field-effect transistors and integrated circuits
Research and development on refractory dielectrics for integrated circuits
Fabrication of a miniature gas chromatograph column using integrated circuit technology was studied and found to be feasible. A bonding problem of forming a strong, gas tight seal between two wafers of silicon has prevented the completion of the column design. Continuing research using tin or a chromium-gold bond promises to overcome the problems of using the proposed gold-eutectic bond. Specifications for the miniature gas chromatograph column are: a spiral capillary column of semi-circular cross section, 30 micron radius, and a total length of 6.9 meters etched into a silicon structure 50 mm in diameter and 0.625 mm thick.
Goddard Space Flight Center has developed a large scale integrated circuit (type 623) which can perform pulse counting, storage, floating point compression, and serial transmission, using a single monolithic device. Counts of 27 or 19 bits can be converted to transmitted values of 12 or 8 bits respectively. Use of the 623 has resulted in substantial savaings in weight, volume, and dollar resources on at least 11 scientific instruments to be flown on 4 NASA spacecraft. The design, construction, and application of the 623 are described.
Report summarizes investigation of single-event upsets (SEU) in bipolar integrated-circuit set of flip-flops (memory cells). Device tested made by advanced digital bipolar silicon process of Honeywell, Inc. Circuit chip contained 4 cells. Construction enabled study of effect of size on SEU behavior. Each cell externally biased so effect of bias current on SEU behavior. Results of study provides important information for optimal design of devices fabricated using buried-layer bipolar process operating in heavy-ion SEU environments. Designers use information to provide required levels of suppression of SEU in specific applications via combinations of size and/or cell-current scaling.
InAlAs/InGaAs heterostructures are studied as multiplier elements for submillimeter-wave monolithic integrated circuits. The designs considered for this purpose are based on the principle of conventional HEMT, HEMT with n+ bottom layer, and a new proposed scheme of quantum-confined modulated charge (QCMC). The QCMC diode is analyzed theoretically and experimentally showing its potential operation capability at 1.5 THz.
This work describes recent progress in the design, processing, and testing of significantly up-scaled 500 C durable 4H-SiC junction field effect transistor (JFET) integrated circuit (IC) technology with two-level interconnect undergoing development at NASA Glenn Research Center. For the first time, stable electrical operation of semiconductor ICs for over one year at 500 C in air atmosphere is reported. These groundbreaking durability results were attained on two-level interconnect JFET demonstration ICs with 175 or more transistors on each chip. This corresponds to a more than 7-fold increase in 500 C-durable circuit complexity from the 24 transistor ring oscillator ICs reported at HiTEC 2016. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for combustion engine sensing and control, planetary exploration, deep-well drilling monitoring, and other harsh-environment applications.
This paper describes the design and development of a set of multifunction VHF/UHF integrated circuits aimed at providing a major improvement in spacecraft radio reliability through low stress operation and the processing of these circuits in beam-lead form. The methods evolved for the high frequency characterization of the devices are discussed together with the design of suitable test fixtures. Typical test results and the distribution of test parameters are presented. A unique carrier for beam-lead devices is described, and the need for such a device is discussed. The application of the carrier to device screening, burn-in and drift measurements is discussed together with the incentives for providing these capabilities. An overview of the integration of the devices into the spacecraft radio is given and candidate assembly processes are discussed. The technology impact of this approach upon future spacecraft radio systems is qualitatively examined.
Advanced processing techniques for fabricating high reliability silicon integrated circuits, and failure mode studies
Automated DC pin to pin test method for effective evaluation and screening of integrated circuits
A review is presented of some features of hybrid integrated circuits that make their use advantageous in miniature biotelemetry applications. The various techniques for fabricating resistors, capacitors and interconnections by both thin film and thick film technology are discussed. The use of chip capacitors, resistors, and especially standard IC chips on substrates with fired-on interconnection patterns is emphasized. The review is designed primarily to acquaint biotelemetry users and designers with an overview of this fabrication technique so that they can better communicate their needs with an understanding of its limitations and advantages to facilities specializing in hybrid construction.
Testing fixture facilitates radio-frequency characterization of microwave and millimeter-wave integrated circuits. Includes base onto which two cosine-tapered ridge waveguide-to-microstrip transitions fastened. Length and profile of taper determined analytically to provide maximum bandwidth and minimum insertion loss. Each cosine taper provides transformation from high impedance of waveguide to characteristic impedance of microstrip. Used in conjunction with automatic network analyzer to provide user with deembedded scattering parameters of device under test. Operates from 26.5 to 40.0 GHz, but operation extends to much higher frequencies.