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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 181 records · Page 10

All sources NASA NTRS DOE OSTI

NASA NTRS2014

A 0.18 micrometer CMOS Thermopile Readout ASIC Immune to 50 MRAD Total Ionizing Dose (SI) and Single Event Latchup to 174MeV-cm(exp 2)/mg

Radiation hardened by design (RHBD) techniques allow commercial CMOS circuits to operate in high total ionizing dose and particle fluence environments. Our radiation hard multi-channel digitizer (MCD) ASIC (Figure 1) is a versatile analog system on a chip (SoC) fabricated in 180nm CMOS. It provides 18 chopper stabilized amplifier channels, a 16- bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The MCD was evaluated at Goddard Space Flight Center and Texas A&M University's radiation effects facilities and found to be immune to single event latchup (SEL) and total ionizing dose (TID) at 174 MeV-cm(exp 2)/mg and 50 Mrad (Si) respectively.

radiation hardened by design↗

NASA NTRS1971

Digital telemetry system eliminates data redundancy

Floating aperature, zero-order predictor /ZOP/ circuit eliminates telemetered data redundancy by examining data from each sensor before it is multiplexed and transmitted. Digital devices to implement design are off-the-shelf items such as gates, registers and flip-flops, which are readily amenable to large-scale integration techniques.

Hymer, R. L.↗

NASA NTRS1980

Development of Boolean calculus and its applications

The development of Boolean calculus for its application to developing digital system design methodologies that would reduce system complexity, size, cost, speed, power requirements, etc., is discussed. Synthesis procedures for logic circuits are examined particularly asynchronous circuits using clock triggered flip flops.

Tapia, M. A.↗

NASA NTRS1981

Commutated automatic gain control system

A commutated automatic gain control system (AGC) was designed and constructed for the prototype Loran C receiver. The AGC is designed to improve the signal-to-signal ratio of the received Loran signals. The AGC design does not require any analog to digital conversion and it utilizes commonly available components. The AGC consists of: (1) a circuit which samples the peak of the envelope of the Loran signal to obtain an AGC voltage for each of three Loran stations, (2) a dc gain circuit to control the overall gain of the AGC system, and (3) an AGC amplification of the input RF signal. The performance of the AGC system was observed in bench and flight tests; it has improved the overall accuracy of the receiver. Improvements in the accuracy of the time difference calculations to within approx. + or - 1.5 microseconds of the observed time differnces for a given position are reported.

Yost, S. R.↗

NASA NTRS1984

Optimum Cyclic Redundancy Codes for Noisier Channels

Binary cyclic redundancy codes for feedback communication over noisy digital links are considered. The standard 16 bit American Data and Computer Communication Protocol (ADCCP) polynomial is designed for digital links which already have a low input bit error probability. For file transfer between personal computers over telephone circuits, the quality of resulting digital circuit may be much lower. The 3 byte (24 bit) and 4 byte (32 bit) polynomials are considered. Generator polynomials of a certain class have minimum weight and yet achieve the bound on minimum distance for arbitrary codes. Particular choices for 24 bit and 32 bit redundancies are exhibited: of weight and distance 6 in the 24-bit case; and weight 10 and distance 8 in the 32-bit case.

Merkey, P.↗

NASA NTRS1984

Optimum cyclic redundancy codes for noisy channels

Merkey, P.↗

NASA NTRS1992

Analog/digital pH meter system I.C.

The project utilizes design automation software tools to design, simulate, and fabricate a pH meter integrated circuit (IC) system including a successive approximation type seven-bit analog to digital converter circuits using a 1.25 micron N-Well CMOS MOSIS process. The input voltage ranges from 0.5 to 1.0 V derived from a special type pH sensor, and the output is a three-digit decimal number display of pH with one decimal point.

Vincent, Paul↗

NASA NTRS2003

Modular, Parallel Pulse-Shaping Filter Architectures

Novel architectures based on parallel subconvolution frequency-domain filtering methods have been developed for modular processing rate reduction of discrete-time pulse-shaping filters. Such pulse-shaping is desirable and often necessary to obtain bandwidth efficiency in very-high-rate wireless communications systems. In principle, this processing could be implemented in very-large-scale integrated (VLSI) circuits. Whereas other approaches to digital pulse-shaping are based primarily on time-domain processing concepts, the theory and design rules of the architectures presented here are founded on frequency-domain processing that has advantages in certain systems.

Gray, Andrew A.↗

NASA NTRS2012

A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

Quilligan, G.↗

DOE OSTI2023

Will Stochastic Devices Play Nice With Others in Neuromorphic Hardware?: There’s More to a Probabilistic System Than Noisy Devices

Achieving brain-like efficiency in computing requires a co-design between the development of neural algorithms, brain-inspired circuit design, and careful consideration of how to use emerging devices. The recognition that leveraging device-level noise as a source of controlled stochasticity represents an exciting prospect of achieving brain-like capabilities in probabilistic neural algorithms, but the reality of integrating stochastic devices with deterministic devices in an already-challenging neuromorphic circuit design process is formidable. Here, we explore how the brain combines different signaling modalities into its neural circuits as well as consider the implications of more tightly integrated stochastic, analog, and digital circuits. Further, by acknowledging that a fully CMOS implementation is the appropriate baseline, we conclude that if mixing modalities is going to be successful for neuromorphic computing, it will be critical that device choices consider strengths and limitations at the overall circuit level.

42 ENGINEERING↗

NASA NTRS2012

A Spacecraft Housekeeping System-on-Chip in a Radiation Hardened Structured ASIC

Housekeeping systems are essential to health monitoring of spacecraft and instruments. Typically, sensors are distributed across various sub-systems and data is collected using components such as analog-to-digital converters, analog multiplexers and amplifiers. In most cases programmable devices are used to implement the data acquisition control and storage, and the interface to higher level systems. Such discrete implementations require additional size, weight, power and interconnect complexity versus an integrated circuit solution, as well as the qualification of multiple parts. Although commercial devices are readily available, they are not suitable for space applications due the radiation tolerance and qualification requirements. The Housekeeping System-o n-A-Chip (HKSOC) is a low power, radiation hardened integrated solution suitable for spacecraft and instrument control and data collection. A prototype has been designed and includes a wide variety of functions including a 16-channel analog front-end for driving and reading sensors, analog-to-digital and digital-to-analog converters, on-chip temperature sensor, power supply current sense circuits, general purpose comparators and amplifiers, a 32-bit processor, digital I/O, pulse-width modulation (PWM) generators, timers and I2C master and slave serial interfaces. In addition, the device can operate in a bypass mode where the processor is disabled and external logic is used to control the analog and mixed signal functions. The device is suitable for stand-alone or distributed systems where multiple chips can be deployed across different sub-systems as intelligent nodes with computing and processing capabilities.

Suarez, George↗

NASA NTRS1973

Digital hydraulic valving system

The design and development are reported of a digital hydraulic valving system that would accept direct digital inputs. Topics include: summary of contractual accomplishments, design and function description, valve parameters and calculations, conclusions, and recommendations. The electrical control circuit operating procedure is outlined in an appendix.

Source record↗

NASA NTRS1989

Programmable rate modem utilizing digital signal processing techniques

The engineering development study to follow was written to address the need for a Programmable Rate Digital Satellite Modem capable of supporting both burst and continuous transmission modes with either binary phase shift keying (BPSK) or quadrature phase shift keying (QPSK) modulation. The preferred implementation technique is an all digital one which utilizes as much digital signal processing (DSP) as possible. Here design tradeoffs in each portion of the modulator and demodulator subsystem are outlined, and viable circuit approaches which are easily repeatable, have low implementation losses and have low production costs are identified. The research involved for this study was divided into nine technical papers, each addressing a significant region of concern in a variable rate modem design. Trivial portions and basic support logic designs surrounding the nine major modem blocks were omitted. In brief, the nine topic areas were: (1) Transmit Data Filtering; (2) Transmit Clock Generation; (3) Carrier Synthesizer; (4) Receive AGC; (5) Receive Data Filtering; (6) RF Oscillator Phase Noise; (7) Receive Carrier Selectivity; (8) Carrier Recovery; and (9) Timing Recovery.

Bunya, George K.↗

NASA NTRS1992

A gallium-arsenide digital phase shifter for clock and control signal distribution in high-speed digital systems

The design, implementation, testing, and applications of a gallium-arsenide digital phase shifter and fan-out buffer are described. The integrated circuit provides a method for adjusting the phase of high-speed clock and control signals in digital systems, without the need for pruning cables, multiplexing between cables of different lengths, delay lines, or similar techniques. The phase of signals distributed with the described chip can be dynamically adjusted in eight different steps of approximately 60 ps per step. The IC also serves as a fan-out buffer and provides 12 in-phase outputs. The chip is useful for distributing high-speed clock and control signals in synchronous digital systems, especially if components are distributed over a large physical area or if there is a large number of components.

Fouts, Douglas J.↗

NASA NTRS1996

Imaging Spectrometer With Liquid-Crystal Tunable Filter

Imaging spectrometer constructed from charged-coupled-device video camera; liquid-crystal tunable filter (LCTF) placed in front of camera lens; and associated digital and analog control, signal-processing, and data-processing circuits. To enable operation of instrument in specific application for which designed (balloon flights in cold weather), camera and LCTF surrounded by electric heating pad. Total operating power, excluding that consumed by heating pad, 16 W. Instrument weighs 4.5 kg.

Chrien, Thomas G.↗

DOE OSTI2023

In-Pixel Readout IC with compact in-pixel ADC for Pixel detectors at HL LHC

The prototype Smart Pixel concept test chip (SP28), designed in a CMOS 28 nm bulk process, is a proof of concept readout integrated circuit (ROIC) designed for a future Phase III High Luminosity upgrade of the Large Hadron Collider. It employs a synchronous analog to digital converter (ADC) for the front-end design, with signal processing and data conversion within a single bunch crossing of 25 ns. It is therefore capable of accurately detecting hits occurring in consecutive bunch crossings, without off-time registration of events and pileup insensitivity, making it particularly suitable for the inner most layers of the vertex detector. The ROIC consists of a matrix of 32 × 16 pixels, each 25 × 25 µm 2 in size. Each pixel contains a charge sensitive preamplifer with leakage current compensation, three auto-zero comparators for a 2-bit fash-type ADC. The total power consumption is approximately 5 µW per pixel. The measured noise at the output of all the hit comparators across the ROIC is < 90 e- with threshold dispersion < 45 e-RMS, which allows an in-time threshold setting of ≈ 475 e-.

Parpillon, Benjamin↗

NASA NTRS1979

The 30/20 GHz mixed user architecture development study: Executive summary

The baseline 30/30 GHz satellite communication system, designed for cost-effective communications in the years 1990 to 2000, incorporates on-board satellite demodulation and routing of individual 64 kbps digital voice-grade circuits. This level of routing flexibility is necessary to provide efficient communications to the large number of direct-to-user terminals (DTU) projected. The circuit interfacing hardware is distributed among all the DTU and master control stations. The switching circuitry which provides full interconnectivity between 30 to 45 thousand circuits is in the satellite. The DTU terminal cost, perhaps the largest element in the system cost, represents the largest economic value element of the system because it avoids using terrestrial signal distribution and routing and the charges associated with these functions. Satellite baseline design and power requirements for the system are examined.

Source record↗

DOE OSTI2021

Strategies for on-chip digital data compression for X-ray pixel detectors

Here, the continued desire for X-ray pixel detectors with higher frame rates will stress the ability of application-specific integrated circuit (ASIC) designers to provide sufficient off-chip bandwidth to reach continuous frame rates in the 1 MHz regime. To move from the current 10 kHz to the 1 MHz frame rate regime, ASIC designers will continue to pack as many power-hungry high-speed transceivers at the periphery of the ASIC as possible. In this paper, however, we present new strategies to make the most efficient use of the off-chip bandwidth by utilizing data compression schemes for X-ray photon-counting and charge-integrating pixel detectors. In particular, we describe a novel in-pixel compression scheme that converts from analog to digital converter units to encoded photon counts near the photon Poisson noise level and achieves a compression ratio of >1.5x independent of the dataset. In addition, we describe a simple yet efficient zero-suppression compression scheme called "zeromask" (ZM) located at the ASIC's edge before streaming data off the ASIC chip. ZM achieves average compression ratios of >4x, >7x, and >8x for high-energy X-ray diffraction, ptychography, and X-ray photon correlation spectroscopy datasets, respectively. We present the conceptual designs, register-transfer level block diagrams, and the physical ASIC implementation of these compression schemes in 65 nm CMOS. When combined, these two digital compression schemes could increase the effective off-chip bandwidth by a factor of 6-12x.

47 OTHER INSTRUMENTATION↗