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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 181 records · Page 10
All sourcesNASA NTRSDOE OSTI
NASA NTRS2008

Integrated Circuit Chip Improves Network Efficiency

Prior to 1999 and the development of SpaceWire, a standard for high-speed links for computer networks managed by the European Space Agency (ESA), there was no high-speed communications protocol for flight electronics. Onboard computers, processing units, and other electronics had to be designed for individual projects and then redesigned for subsequent projects, which increased development periods, costs, and risks. After adopting the SpaceWire protocol in 2000, NASA implemented the standard on the Swift mission, a gamma ray burst-alert telescope launched in November 2004. Scientists and developers on the James Webb Space Telescope further developed the network version of SpaceWire. In essence, SpaceWire enables more science missions at a lower cost, because it provides a standard interface between flight electronics components; new systems need not be custom built to accommodate individual missions, so electronics can be reused. New protocols are helping to standardize higher layers of computer communication. Goddard Space Flight Center improved on the ESA-developed SpaceWire by enabling standard protocols, which included defining quality of service and supporting plug-and-play capabilities. Goddard upgraded SpaceWire to make the routers more efficient and reliable, with features including redundant cables, simultaneous discrete broadcast pulses, prevention of network blockage, and improved verification. Redundant cables simplify management because the user does not need to worry about which connection is available, and simultaneous broadcast signals allow multiple users to broadcast low-latency side-band signal pulses across the network using the same resources for data communication. Additional features have been added to the SpaceWire switch to prevent network blockage so that more robust networks can be designed. Goddard s verification environment for the link-and-switch implementation continuously randomizes and tests different parts, constantly anticipating situations, which helps improve communications reliability. It has been tested in many different implementations for compatibility.

Source record↗
DOE OSTI2014

Combining nanocalorimetry and dynamic transmission electron microscopy for in situ characterization of materials processes under rapid heating and cooling

Nanocalorimetry is a chip-based thermal analysis technique capable of analyzing endothermic and exothermic reactions at very high heating and cooling rates. Here, we couple a nanocalorimeter with an extremely fast in situ microstructural characterization tool to identify the physical origin of rapid enthalpic signals. More specifically, we describe the development of a system to enable in situ nanocalorimetry experiments in the dynamic transmission electron microscope (DTEM), a time-resolved TEM capable of generating images and electron diffraction patterns with exposure times of 30 ns–500 ns. The full experimental system consists of a modified nanocalorimeter sensor, a custom-built in situ nanocalorimetry holder, a data acquisition system, and the DTEM itself, and is capable of thermodynamic and microstructural characterization of reactions over a range of heating rates (10{sup 2} K/s–10{sup 5} K/s) accessible by conventional (DC) nanocalorimetry. To establish its ability to capture synchronized calorimetric and microstructural data during rapid transformations, this work describes measurements on the melting of an aluminum thin film. We were able to identify the phase transformation in both the nanocalorimetry traces and in electron diffraction patterns taken by the DTEM. Potential applications for the newly developed system are described and future system improvements are discussed.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

3D-printed micro ion trap technology for quantum information applications

Trapped-ion applications, such as in quantum information processing1, precision measurements, optical clocks and mass spectrometry, rely on specialized high-performance ion traps. The last three of these applications typically use traditional machining to customize macroscopic 3D Paul traps, whereas quantum information processing experiments usually rely on photolithographic techniques to miniaturize the traps and meet scalability requirements. Using photolithography, however, it is challenging to fabricate the complex 3D electrode structures required for optimal confinement. Here, in this work, we demonstrate a high-resolution 3D printing technology based on two-photon polymerization (2PP) that is capable of fabricating large arrays of high-performance miniaturized 3D traps. We show that 3D-printed ion traps combine the advantages, such as strong radial confinement, of traditionally machined 3D traps with on-chip miniaturization. We trap calcium ions in 3D-printed ion traps with radial trap frequencies ranging from 2 MHz to 24 MHz. The tight confinement eases ion cooling requirements and allows us to implement high-quality Rabi oscillations with Doppler cooling only. Also, we demonstrate a two-qubit gate with a Bell-state fidelity of 0.978 ± 0.012. With 3D printing technology, the design freedom is greatly expanded without sacrificing scalability and precision, so that ion trap geometries can be optimized for higher performance and better functionality.

quantum information↗
NASA NTRS2015

Body of Knowledge (BOK) for Copper Wire Bonds

Copper wire bonds have replaced gold wire bonds in the majority of commercial semiconductor devices for the latest technology nodes. Although economics has been the driving mechanism to lower semiconductor packaging costs for a savings of about 20% by replacing gold wire bonds with copper, copper also has materials property advantages over gold. When compared to gold, copper has approximately: 25% lower electrical resistivity, 30% higher thermal conductivity, 75% higher tensile strength and 45% higher modulus of elasticity. Copper wire bonds on aluminum bond pads are also more mechanically robust over time and elevated temperature due to the slower intermetallic formation rate - approximately 1/100th that of the gold to aluminum intermetallic formation rate. However, there are significant tradeoffs with copper wire bonding - copper has twice the hardness of gold which results in a narrower bonding manufacturing process window and requires that the semiconductor companies design more mechanically rigid bonding pads to prevent cratering to both the bond pad and underlying chip structure. Furthermore, copper is significantly more prone to corrosion issues. The semiconductor packaging industry has responded to this corrosion concern by creating a palladium coated copper bonding wire, which is more corrosion resistant than pure copper bonding wire. Also, the selection of the device molding compound is critical because use of environmentally friendly green compounds can result in internal CTE (Coefficient of Thermal Expansion) mismatches with the copper wire bonds that can eventually lead to device failures during thermal cycling. Despite the difficult problems associated with the changeover to copper bonding wire, there are billions of copper wire bonded devices delivered annually to customers. It is noteworthy that Texas Instruments announced in October of 2014 that they are shipping microcircuits containing copper wire bonds for safety critical automotive applications. An evaluation of copper wire bond technology for applicability to spaceflight hardware may be warranted along with concurrently compiling a comprehensive understanding of the failure mechanisms involved with copper wire bonded semiconductor devices.

Body of Knowledge (BOK)↗
DOE OSTI2013

A 15GSa/s, 1.5GHz bandwidth waveform digitizing ASIC

The PSEC4 custom integrated circuit was designed for the recording of fast waveforms for use in large-area time-of-flight detector systems. The ASIC has been fabricated using the IBM-8RF 0.13 micron CMOS process. On each of 6 analog channels, PSEC4 employs a switched capacitor array (SCA) 256 samples deep, a ramp-compare ADC with 10.5 bits of DC dynamic range, and a serial data readout with the capability of region-of-interest windowing to reduce dead time. The sampling rate can be adjusted between 4 and 15 Gigasamples/second [GSa/s] on all channels and is servo-controlled on-chip with a low-jitter delay-locked loop (DLL). The input signals are passively coupled on-chip with a -3 dB analog bandwidth of 1.5 GHz. The power consumption in quiescent sampling mode is less than 50 mW/chip; at a sustained trigger and readout rate of 50 kHz the chip draws 100 mW. After fixed-pattern pedestal subtraction, the uncorrected integral non-linearity is 0.15% over an 750 mV dynamic range. With a linearity correction, a full 1 V signal voltage range is available.The sampling timebase has a fixed-pattern non-linearity with an RMS of 13%, which can be corrected for precision waveform feature extraction and timing.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS2024

COLUTA: Custom 8-Channel 15-bit 40-MSPS ADC for the ATLAS Liquid Argon Calorimeter Readout

The stringent radiation-tolerance, quantization requirements, and the need for seamless integration of the on-detector readout electronics chain require the design of a full-custom analog-to-digital converter (ADC) for the 182,468 channels in the ATLAS Liquid Argon (LAr) calorimeter at the Large Hadron Collider (LHC) at CERN, as part of the High-Luminosity LHC (HL-LHC) upgrade. Each of the 8 channels in the prototype 65 nm CMOS ADC with 15-bit resolution and >68 dB signal-to-noise-and-distortion ratio (SNDR), or equivalently >11 effective number of bits (ENOB), consists of a Multiplying-DAC (MDAC) and a successive-approximation (SAR) ADC. A digital data processing unit (DDPU) calibrates and serially transmits the quantized data. Initial lab characterization of 18 chips shows a minimum SNDR of 69.5 dB at full-scale at about 5 MHz and a maximum power consumption of 1.17 W; differential non-linearity (DNL) measurements show no missing codes. Additional validation of the ADC is ongoing before approximately 70k chips can be mass-produced for the upgrade.

Rui Xu↗
NASA NTRS1996

Hypercars: The next industrial revolution

The auto industry -- one-seventh of the GNP, and the highest expression of the Iron Age -- is about to trigger the biggest transformation in industrial structure since the microchip. Ultralight cars molded from net-shape advanced composites can be several-fold lighter than present steel cars, yet safer, sportier, and more comfortable, durable, and beautiful. Modern hybrid-electric drives boost efficiency approximately 1.3-1.5x in heavy steel cars, but approximately 5-20x in ultralight, very slippery plafforms. Synergistically combined into ultralight-hybrid 'hypercars,' these elements can yield state-of-the-shelf family cars that average 150-300+ mi/gal -- twice that with state-of-the-art technologies -- yet can also be superior in all other respects, probably including cost: carbon-fiber monocoques can actually be cheaper to mass-produce that steel unibodies. Designing cars more like aircraft and less like tanks requires not only an approximately 400-500 kg curb mass and very low air and road drag, but also an aerospace philosophy of engineering integration. Mass, cost, and complexity turn out to compound with heavy hybrids but to decompound with ultralight hybrids, owing partly to radical simplification. Excellent aerodynamics, preferable including advanced techniques for passive boundary-layer control, will be the key to successful design integration. Transforming automaking is a competitive and environmental imperative, could form the nucleus of a green industrial Renaissance, and would enhance national security by, among other things, saving as much oil as OPEC now extracts. However, this transformation faces serious cultural barriers. For example, hypercars will be more like computers with wheels than like cars with chips -- they'll have an order of magnitude more code than today's cars -- but Detroit is not a software culture. Just the transition from stamped and welded steel to integrated and adhesive-joined synthetics is difficult enough. Nonetheless, hypercars are rapidly heading to market in the late 1990s, because approximately 25 current and intending automakers are eager to capture their potentially decisive competitive advantages -- including order-of-magnitude reductions in product cycle time, tooling cost, assembly effort, and parts count. Hypercars will succeed, and may well sweep the market, not because of mandates or subsidies, but because of manufacturers' quest for competitive advantage and customers' desire for better, smarter cars.

Lovins, Amory B.↗
NASA NTRS2010

Reconfigurable Hardware for Compressing Hyperspectral Image Data

High-speed, low-power, reconfigurable electronic hardware has been developed to implement ICER-3D, an algorithm for compressing hyperspectral-image data. The algorithm and parts thereof have been the topics of several NASA Tech Briefs articles, including Context Modeler for Wavelet Compression of Hyperspectral Images (NPO-43239) and ICER-3D Hyperspectral Image Compression Software (NPO-43238), which appear elsewhere in this issue of NASA Tech Briefs. As described in more detail in those articles, the algorithm includes three main subalgorithms: one for computing wavelet transforms, one for context modeling, and one for entropy encoding. For the purpose of designing the hardware, these subalgorithms are treated as modules to be implemented efficiently in field-programmable gate arrays (FPGAs). The design takes advantage of industry- standard, commercially available FPGAs. The implementation targets the Xilinx Virtex II pro architecture, which has embedded PowerPC processor cores with flexible on-chip bus architecture. It incorporates an efficient parallel and pipelined architecture to compress the three-dimensional image data. The design provides for internal buffering to minimize intensive input/output operations while making efficient use of offchip memory. The design is scalable in that the subalgorithms are implemented as independent hardware modules that can be combined in parallel to increase throughput. The on-chip processor manages the overall operation of the compression system, including execution of the top-level control functions as well as scheduling, initiating, and monitoring processes. The design prototype has been demonstrated to be capable of compressing hyperspectral data at a rate of 4.5 megasamples per second at a conservative clock frequency of 50 MHz, with a potential for substantially greater throughput at a higher clock frequency. The power consumption of the prototype is less than 6.5 W. The reconfigurability (by means of reprogramming) of the FPGAs makes it possible to effectively alter the design to some extent to satisfy different requirements without adding hardware. The implementation could be easily propagated to future FPGA generations and/or to custom application-specific integrated circuits.

Aranki, Nazeeh↗
NASA NTRS1995

Advanced packaging for Integrated Micro-Instruments

The relationship between packaging, microelectronics, and micro-electrical-mechanical systems (MEMS) is an important one, particularly when the edges of performance boundaries are pressed, as in the case of miniaturized systems. Packaging is a sort of physical backbone that enables the maximum performance of these systems to be realized, and the penalties imposed by conventional packing approaches is particularly limiting for MEMS devices. As such, advanced packaging approaches, such as multi-chip modules (MCM's) have been touted as a true means of electronic 'enablement' for a variety of application domains. Realizing an optimum system of packaging, however, in not as simple as replacing a set of single chip packages with a substrate of interconnections. Research at Phillips Laboratory has turned up a number of integrating options in the two- and three-dimensional rending of miniature systems with physical interconnection structures with intrinsically high performance. Not only do these structures motivate the redesign of integrated circuits (IC's) for lower power, but they possess interesting features that provide a framework for the direct integration of MEMS devices. Cost remains a barrier to the application of MEMS devices, even in space systems. Several innovations are suggested that will result in lower cost and more rapid cycle time. First, the novelty of a 'constant floor plan' MCM which encapsulates a variety of commonly used components into a stockable, easily customized assembly is discussed. Next, the use of low-cost substrates is examined. The anticipated advent of ultra-high density interconnect (UHDI) is suggested as the limit argument of advanced packaging. Finally, the concept of a heterogeneous 3-D MCM system is outlined that allows for the combination of different compatible packaging approaches into a uniformly dense structure that could also include MEMS-based sensors.

Lyke, James L.↗
DOE OSTI2019

Integrated high electron mobility transistors in GaAs/AlGaAs heterostructures for amplification at sub-Kelvin temperatures

Here, we demonstrate the use of custom high electron mobility transistors (HEMTs) fabricated in GaAs/AlGaAs heterostructures to amplify current from quantum dot devices. The amplifier circuit is located adjacent to the quantum dot device, at sub-Kelvin temperatures, in order to reduce the impact of cable capacitance and environmental noise. Using this circuit, we show a current gain of 380 for 0.56 μW of power dissipation, with a bandwidth of 2.7 MHz and current noise referred to the input of 24 fA/Hz 1/2 for frequencies of 0.1–1 MHz. The power consumption required for similar gain is reduced by more than a factor of 20 compared to a previous demonstration using a commercial off-the-shelf HEMT. Lastly, we also demonstrate integration of a HEMT amplifier circuit on-chip with a quantum dot device, which has the potential to reduce parasitics and should allow for more complex circuits with reduced footprints.

42 ENGINEERING↗
DOE OSTI2019

Near-field photonic cooling through control of the chemical potential of photons

Photonic cooling of matter has enabled both access to unexplored states of matter, such as Bose–Einstein condensates, and novel approaches to solid-state refrigeration. Critical to these photonic cooling approaches is the use of low-entropy coherent radiation from lasers, which makes the cooling process thermodynamically feasible. Recent theoretical work has suggested that photonic solid-state cooling may be accomplished by tuning the chemical potential of photons without using coherent laser radiation, but such cooling has not been experimentally realized. Here we report an experimental demonstration of photonic cooling without laser light using a custom-fabricated nanocalorimetric device and a photodiode. Here, we show that when they are in each other’s near-field—that is, when the size of the vacuum gap between the planar surfaces of the calorimetric device and a reverse-biased photodiode is reduced to tens of nanometres—solid-state cooling of the calorimetric device can be accomplished via a combination of photon tunnelling, which enhances the transport of photons across nanoscale gaps, and suppression of photon emission from the photodiode due to a change in the chemical potential of the photons under an applied reverse bias. This demonstration of active nanophotonic cooling—without the use of coherent laser radiation—lays the experimental foundation for systematic exploration of nanoscale photonics and optoelectronics for solid-state refrigeration and on-chip device cooling.

77 NANOSCIENCE AND NANOTECHNOLOGY↗
DOE OSTI2016

SU-G-201-08: Energy Response of Thermoluminescent Microcube Dosimeters in Water for Kilovoltage X-Ray Beams

Purpose: To characterize the energy dependence for TLD-100 microcubes in water at kilovoltage energies. Methods: TLD-100 microcubes with dimensions of (1 × 1 × 1) mm{sup 3} were irradiated with kilovoltage x-rays in a custom-built thin-window liquid water phantom. The TLD-100 microcubes were held in Virtual Water™ probes and aligned at a 2 cm depth in water. Irradiations were performed using the M-series x-ray beams of energies ranging from 50-250 kVp and normalized to a {sup 60}Co beam located at the UWADCL. Simulations using the EGSnrc Monte Carlo Code System were performed to model the x-ray beams, the {sup 60}Co beam, the water phantom and the dosimeters in the phantom. The egs-chamber user code was used to tally the dose to the TLDs and the dose to water. The measurements and calculations were used to determine the intrinsic energy dependence, absorbed-dose energy dependence, and absorbed-dose sensitivity. These values were compared to TLD-100 chips with dimensions of (3.2 × 0.9 × 0.9) mm{sup 3}. Results: The measured TLD-100 microcube response per dose to water among all investigated x-ray energies had a maximum percent difference of 61% relative to {sup 60}Co. The simulated ratio of dose to water to the dose to TLD had a maximum percent difference of 29% relative to {sup 60}Co. The ratio of dose to TLD to the TLD output had a maximum percent difference of 13% relative to {sup 60}Co. The maximum percent difference for the absorbed-dose sensitivity was 15% more than the used value of 1.41. Conclusion: These results confirm that differences in beam quality have a significant effect on TLD response when irradiated in water. These results also indicated a difference in TLD-100 response between microcube and chip geometries. The intrinsic energy dependence and the absorbed-dose energy dependence deviated up to 10% between TLD-100 microcubes and chips.

60 APPLIED LIFE SCIENCES↗
NASA NTRS1987

IRAC test report. Gallium doped silicon band 2: Read noise and dark current

A direct readout infrared detector array, a candidate for the Space Infrared Telescope Facility (SIRTF) Infrared Array Camera (IRAC), has been tested. The array has a detector surface of gallium doped silicon, bump bonded to a 58x62 pixel MOSFET multiplexer on a separate chip. Although this chip and system do not meet all the SIRTF requirements, the critically important read noise is within a factor of 3 of the requirement. Significant accomplishments of this study include: (1) development of a low noise correlated double sampling readout system with a readout noise of 127 to 164 electrons (based on the detector integrator capacitance of 0.1 pF); (2) measurement of the readout noise of the detector itself, ranging from 123 to 214 electrons with bias only (best to worst pixel), and 256 to 424 electrons with full clocking in normal operation at 5.4 K where dark current is small. Thirty percent smaller read noises are obtained at a temperature of 15K; (3) measurement of the detector response versus integration time, showing significant nonlinear behavior for large signals, well below the saturation level; and (4) development of a custom computer interface and suitable software for collection, analysis and display of data.

Lamb, Gerald↗
DOE OSTI2022

The Octopus processor for the CMS L1 muon trigger for High Luminosity LHC

The upgraded L1 muon trigger system of the CMS experiment in the High Luminosity Large Hadron Collider is based on custom processors featuring large Field Programmable Gate Arrays (FPGAs) connected by large numbers of optical links. These provide the I/O bandwidth and power necessary to process the complex algorithms used during the collection of physics data. The design and performance requirements of these processors creates significant challenges in signal integrity, power delivery, and thermal management. In this paper we describe the Octopus processor, featuring a large Xilinx Virtex Ultrascale+ FPGA and up to 128 links interfaced to optics through high quality twin-ax copper cables. Results on signal integrity at 25 Gb/s and the first demonstration of 50+ Gb/s links with pluggable optics in CMS are also shown, demonstrating bit error rates below 10 –15 at a 95% confidence level. The thermal performance is measured inside an Advanced-TCA crate with acceptable thermal margins up to 200 W of chip power. Future improvements are mentioned, potentially allowing operation at up to 300 W.

Instruments & Instrumentation↗
DOE OSTI2024

DIRECT RF SAMPLING BASED LLRF CONTROL SYSTEM FOR C-BAND LINEAR ACCELERATOR

Low Level RF (LLRF) control systems of linear accel- erators (LINACs) are typically implemented with hetero- dyne based architectures, which have complex analog RF mixers for up and down conversion. The Gen 3 Radio Fre- quency System-on-Chip (RFSoC) device from AMD Xilinx integrates data converters with maximum RF frequency of 6 GHz. This enables direct RF sampling of C-band LLRF signal typically operated at 5.712 GHz without any analogue mixers, which can significantly simplify the system architec- ture. The data converters sample RF signals in higher order Nyquist zones and then up or down convert digitally by the integrated data path in RFSoC. The closed-loop feedback control firmware implemented in FPGA integrated in RF- SoC can process the base-band signal from the ADC data path and calculate the updated phase and amplitude to be up- mixed by the DAC data path. We have developed a C-band LLRF control RFSoC platform with direct RF sampling, which targets Cool Copper Collider (𝐶3) and other C or S band LINAC research and development projects. In this paper, the architecture of the platform will be described. We have optimized the configuration of the data converter and characterized performance of them with RF pulses. The test results for some of the key performance parameters for the LLRF platform with our custom solid-state amplifier, such as phase and amplitude stability, will be discussed in this paper.

Liu, C↗
NASA NTRS2006

X-Ray Detector Research at MSFC for Space Applications

NASA's Vision for Space Exploration has specific goals aimed at exploring the Solar System. This vision, under presidential mandate includes landing humans on the moon before the end of the next decade, paving the way for eventual journeys to Mars and beyond. The first missions to the moon will be in the form of both Orbiters and Landers, with the goal of paving the way for human return. One of the instruments we are currently working on,in collaboration with Brookhaven National Laboratory, is a lunar orbiter fluorescent x-ray spectrometer to finely map the light elements (down to Carbon) on surface of the moon. Funded NASA s Planetary Instrument Definition and Development Program the instrument is based on silicon drift detector arrays read out by custom ASICs. These offer the promise of high spectral resolution, necessary for resolving weak lines against a strong background continuum, and very low power requirements, necessary for large areas (greater than 500 square centimeters) required for future lunar missions. Further, the inherent radiation hardness of these detectors makes them ideal candidates for exploring the Jovian system, where the harsh radiation environment from Jupiter s radiation belts creates unfavorable detector conditions. Looking beyond our solar system, in the hard x-ray regime (20-80keV.), we are studying Cadmium-Zinc-Telluride pixilated detectors as feasible candidates for focal plane detectors of a hard x-ray telescope. This energy region bridges the gap between thermal and non-thermal x-ray emission from astronomical sources, will allow us to better understand supernovae nucleosynthesis (such as through the Ti-44 lines at 68keV and 78keV), Active Galactic Nuclei and other compact objects, more completely. The detectors that we are characterizing are 2mm in thickness and are pixilated with a 16x16 array of 300 micrometer pitch pixels (50micometer gap). These detectors are designed at Rutherford Appleton Laboratory, material is from eV Products, and polymer flip-chip assembly was performed by a commercial vendor. An energy resolution of 2.0% at 60keV (or better) should allow us to sufficiently distinguish lines of interest from background continuum, and the detector spatial resolution should be fine enough to over-sample the focal spot from the x-ray focusing optics by about a factor of two. Full technical details of these developments will be presented.

Gaskin, Jessica↗
DOE OSTI2019

A Reconfigurable In Vitro Model for Studying the Blood–Brain Barrier

Much of what is currently known about the role of the blood–brain barrier (BBB) in regulating the passage of chemicals from the blood stream to the central nervous system (CNS) comes from animal in vivo models (requiring extrapolation to human relevance) and 2D static in vitro systems, which fail to capture the rich cell–cell and cell–matrix interactions of the dynamic 3D in vivo tissue microenvironment. In this work we have developed a BBB platform that allows for a high degree of customization in cellular composition, cellular orientation, and physiologically-relevant fluid dynamics. The system characterized and presented in this study reproduces key characteristics of a BBB model (e.g. tight junctions, efflux pumps) allowing for the formation of a selective and functional barrier. We demonstrate that our in vitro BBB is responsive to both biochemical and mechanical cues. This model further allows for culture of a CNS-like space around the BBB. As a result, the design of this platform is a valuable tool for studying BBB function as well as for screening of novel therapeutics.

42 ENGINEERING↗
NASA NTRS2003

Command Interface ASIC - Analog Interface ASIC Chip Set

A command interface application-specific integrated circuit (ASIC) and an analog interface ASIC have been developed as a chip set for remote actuation and monitoring of a collection of switches, which can be used to control generic loads, pyrotechnic devices, and valves in a high-radiation environment. The command interface ASIC (CIA) can be used alone or in combination with the analog interface ASIC (AIA). Designed primarily for incorporation into spacecraft control systems, they are also suitable for use in high-radiation terrestrial environments (e.g., in nuclear power plants and facilities that process radioactive materials). The primary role of the CIA within a spacecraft or other power system is to provide a reconfigurable means of regulating the power bus, actuating all valves, firing all pyrotechnic devices, and controlling the switching of power to all switchable loads. The CIA is a mixed-signal (analog and digital) ASIC that includes an embedded microcontroller with supporting fault-tolerant switch control and monitoring circuitry that is capable of connecting to a redundant set of interintegrated circuit (I(sup 2)C) buses. Commands and telemetry requests are communicated to the CIA. Adherence to the I(sup 2)C bus standard helps to reduce development costs by facilitating the use of previously developed, commercially available components. The AIA is a mixed-signal ASIC that includes the analog circuitry needed to connect the CIA to a custom higher powered version of the I(sup 2)C bus. The higher-powered version is designed to enable operation with bus cables longer than those contemplated in the I(sup 2)C standard. If there are multiple higher-power I(sup 2)C-like buses, then there must an AIA between the CIA and each such bus. The AIA includes two identical interface blocks: one for the side-A I(sup 2)C clock and data buses and the other for the side B buses. All the AIAs on each side are powered from a common power converter module (PCM). Sides A and B of the I(sup 2)C buses are electrically isolated from each other (see figure). They are also isolated from the CIA by use of transformer coupling of signals between the AIA blocks and the CIA.

Ruiz, Baldes↗