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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 181 records · Page 10
All sourcesNASA NTRSDOE OSTI
DOE OSTI2024

Grid Forming Inverter With Increased Short-Circuit Contribution to Address Inverter-Based Microgrid Protection Challenges

Substantial differences in fault levels between grid-tied and islanded modes is one of the primary challenges of microgrid protection. During grid-tied mode, the bulk grid provides significant short-circuit, while during islanded operation the short-circuit magnitude is small due to inverter-based resources limiting their current output close to nominal ratings. Consequently, conventional distribution protection strategies based on overcurrent cannot reliably protect microgrids when operating in islanded mode. Fuses and circuit breakers are particularly affected because of their inverse characteristics. Presently, the absence of affordable solutions for protecting microgrids in islanded mode leads to microgrids shutting down during electrical faults. The contribution of this article is two-fold. The first innovation proposes specific hardware modifications to grid-forming inverters to increase their short-circuit current during electrical faults. The second innovation introduces a novel control strategy designed to preserve control stability margins even when the grid-filter saturates, ensuring sinusoidal output currents under normal and fault conditions. Through experimental results, the inverter with the proposed modifications can provide more than three-times its nominal current during electrical faults. For the prototype testbed, this was sufficient to enable the use of traditional legacy overcurrent protection, achieving the fuse-to-relay and relay-to-relay minimum coordination time for the line-to-ground, line-to-line to ground, and three-phase electrical faults.

42 ENGINEERING↗
NASA NTRS1990

Neural net diagnostics for VLSI test

This paper discusses the application of neural network pattern analysis algorithms to the IC fault diagnosis problem. A fault diagnostic is a decision rule combining what is known about an ideal circuit test response with information about how it is distorted by fabrication variations and measurement noise. The rule is used to detect fault existence in fabricated circuits using real test equipment. Traditional statistical techniques may be used to achieve this goal, but they can employ unrealistic a priori assumptions about measurement data. Our approach to this problem employs an adaptive pattern analysis technique based on feedforward neural networks. During training, a feedforward network automatically captures unknown sample distributions. This is important because distributions arising from the nonlinear effects of process variation can be more complex than is typically assumed. A feedforward network is also able to extract measurement features which contribute significantly to making a correct decision. Traditional feature extraction techniques employ matrix manipulations which can be particularly costly for large measurement vectors. In this paper we discuss a software system which we are developing that uses this approach. We also provide a simple example illustrating the use of the technique for fault detection in an operational amplifier.

Lin, T.↗
DOE OSTI2025

ASDF: A Compiler for Qwerty, a Basis-Oriented Quantum Programming Language

Qwerty is a high-level quantum programming language built on bases and functions rather than circuits. This new paradigm introduces new challenges in compilation, namely synthesizing circuits from basis translations and automatically specializing adjoint or predicated forms of functions. This paper presents ASDF, an open-source compiler for Qwerty that answers these challenges in compiling basis-oriented languages. Enabled with a novel high-level quantum IR implemented in the MLIR framework, our compiler produces OpenQASM 3 or QIR for either simulation or execution on hardware. Our compiler is evaluated by comparing the fault-tolerant resource requirements of generated circuits with other compilers, finding that ASDF produces circuits with comparable cost to prior circuit-oriented compilers.

Adams, Austin J [Georgia Tech]↗
DOE OSTI2022

Understanding Power Systems Protection in the Clean Energy Future

Wind and solar power and battery energy storage are often referred to as inverter-based resources (IBRs), which means they rely on power electronics (inverters) to generate grid-compatible electricity. This is unlike the fossil, nuclear, and hydroelectric plants that use spinning synchronous generators that have provided nearly all U.S. electricity until recently. Synchronous generators can inherently provide several services used to maintain a safe and stable grid and as they are replaced with IBRs it becomes important to understand how these services can be provided. One of these services is fault current, or the ability to inject large amounts of current during a short circuit. This current can easily be detected with low-cost equipment such as circuit breakers. IBRs do not inherently produce large amounts of fault current, and this may eventually require finding alternative sources of fault current or new system protection schemes. This document describes several alternative approaches to maintaining fault current protection and provide a safe, reliable power grid.

14 SOLAR ENERGY↗
NASA NTRS2005

LC Circuits for Diagnosing Embedded Piezoelectric Devices

A recently invented method of nonintrusively detecting faults in piezoelectric devices involves measurement of the resonance frequencies of inductor capacitor (LC) resonant circuits. The method is intended especially to enable diagnosis of piezoelectric sensors, actuators, and sensor/actuators that are embedded in structures and/or are components of multilayer composite material structures.

Chattin, Richard L.↗
DOE OSTI2021

DC Circuit Breakers: A Technology Development Status Survey

DC circuit breakers (DCCBs) play a significant role in obtaining the reliability and stability of DC power systems. Selective and fast isolating of faults minimizes the power supply outages to end electricity users and protects the power converters implemented in the DC system. During the last decades, DCCBs have been deeply investigated in industry and academia. There has been impressive progress in terms of efficiency, response time, power-density, lifetime, and electrical operating ratings. Introducing wide bandgap (WBG) devices further has motivated researchers to propose more efficient and novel topologies. This paper provides a point of reference and a background review for DCCBs from novel aspects, fulfilling absent parts in the literature. The elaborated subjects include current commutation circuitry, DCCBs trip-curves developments, newly added functions to DCCBs, as well as marketing analysis. The advancements of DCCBs are surveyed and development needs are recognized. This paper aims to identify the future research needs of DCCBs for emerging DC power systems.

42 ENGINEERING↗
NASA NTRS1980

Leveling circuits and crustal movements

An investigation of further possible vertical crustal movements in the Western United States made with circuit microclosure analysis is presented. The San Andreas fault in Cal., the Nevada seismic zone in Nev., and the Sierra Nevada in Calif. were studied based on supposition that in areas undergoing crustal movement the misclosure for a particular circuit should have the smallest value when the circuit is formed from the most temporarily homogeneous survey data; it should have larger, predictable values when the circuit is closed with surveys conducted at other times. Leveling surveys along the San Andreas fault and the Nevada seismic zone are discussed, noting the possibility of regional tilting in the Great Basin between 1934 and 1955, and of elevation changes in the Northern Nevada Range using results of leveling surveys between Roseville, Cal. and Reno, Nev.

Chi, S. C.↗
NASA NTRS1983

Fault detection, isolation and reconfiguration in FTMP Methods and experimental results

The Fault-Tolerant Multiprocessor (FTMP) is a highly reliable computer designed to meet a goal of 10 to the -10th failures per hour and built with the objective of flying an active-control transport aircraft. Fault detection, identification, and recovery software is described, and experimental results obtained by injecting faults in the pin level in the FTMP are presented. Over 21,000 faults were injected in the CPU, memory, bus interface circuits, and error detection, masking, and error reporting circuits of one LRU of the multiprocessor. Detection, isolation, and reconfiguration times were recorded for each fault, and the results were found to agree well with earlier assumptions made in reliability modeling.

Lala, J. H.↗
NASA NTRS1990

Model authoring system for fail safe analysis

The Model Authoring System is a prototype software application for generating fault tree analyses and failure mode and effects analyses for circuit designs. Utilizing established artificial intelligence and expert system techniques, the circuits are modeled as a frame-based knowledge base in an expert system shell, which allows the use of object oriented programming and an inference engine. The behavior of the circuit is then captured through IF-THEN rules, which then are searched to generate either a graphical fault tree analysis or failure modes and effects analysis. Sophisticated authoring techniques allow the circuit to be easily modeled, permit its behavior to be quickly defined, and provide abstraction features to deal with complexity.

Sikora, Scott E.↗
DOE OSTI2024

IBR Short Circuit Modeling in ETAP

Mohammad Zadeh from ETAP presented various modeling improvements that included the following: • Address convergence issues by using complete Norton Equivalent model including the IBR series filter impedance. • Fault ride through identification within iterations while short circuit results have not been converged and how that may impact final SC results. • Options for FRT curve 1- using a timer to lock FRT logic vs a hysteresis in FRT curve to avoid unwanted toggling. • Report recent co-operation between software vendors (Aspen, CAPE and ETAP) for adopting a C++ interface for IBR blackbox SC modeling. There was lot of interest to know about the model improvements that are being considered.

24 POWER TRANSMISSION AND DISTRIBUTION↗
NASA NTRS1979

Cable-fault locator

Inexpensive system automatically indicates location of short-circuited section of power cable. Monitor does not require that cable be disconnected from its power source or that test signals be applied. Instead, ground-current sensors are installed in manholes or at other selected locations along cable run. When fault occurs, sensors transmit information about fault location to control center. Repair crew can be sent to location and cable can be returned to service with minimum of downtime.

Cason, R. L.↗
DOE OSTI2023

Active Fault Current Limiting Control for Half-Bridge MMC in HVDC Systems

DC faults of MMC can result in a significantly large fault current due to the discharge of submodule capacitors. The fault current not only risks damaging the MMC but also demands a considerable breaking capacity from the dc circuit breaker (DCCBs). This paper introduces two novel active fault current limiting methods (AFCLs), namely virtual impedance-based and energy control-based AFCL. The first method utilizes circulating current feedforward, which introduces a virtual arm impedance to suppress the rate of rise of the fault current. Meanwhile, the second method relies on the control of the internally stored energy of the MMC to automatically minimize the number of submodules that discharge during a dc-side fault. Therefore, both the dc-side current and the MMC arm current can be effectively suppressed after the occurrence of the fault. The proposed methods do not require fault detection and their response is proportional to the rate of rise in the fault current. Simulation case studies are presented to demonstrate the proposed methods.

active current limiting control↗
NASA NTRS1982

On implementing self-checking microprocessors

A simple and general model of the interfaces and check circuits used for comparing and detecting faults in a pair of 16-bit processors is described, and problems encountered in the application of TI 9900 processors are discussed. The greatest incompatibility is found to lie between the rollback structures of the CPUs and the interface and check logic (ICL) model. The ICL model generates a reset when an error is detected, and a rollback is expected to occur when it is released. The TI 9900 requires a reset of minimum duration, and after release goes through an initialization cycle, obtains rollback parameters from fixed memory locations, and executes the rollback, consistent with the ICL. The ICL is relatively simple, having a complexity equivalent to fewer than 1000 gates.

Rennels, D. A.↗
NASA NTRS1988

Knowledge-based operation and management of communications systems

Expert systems techniques are being applied in operation and control of the Defense Communications System (DCS), which has the mission of providing reliable worldwide voice, data and message services for U.S. forces and commands. Thousands of personnel operate DCS facilities, and many of their functions match the classical expert system scenario: complex, skill-intensive environments with a full spectrum of problems in training and retention, cost containment, modernization, and so on. Two of these functions are: (1) fault isolation and restoral of dedicated circuits at Tech Control Centers, and (2) network management for the Defense Switched Network (the modernized dial-up voice system currently replacing AUTOVON). An expert system for the first of these is deployed for evaluation purposes at Andrews Air Force Base, and plans are being made for procurement of operational systems. In the second area, knowledge obtained with a sophisticated simulator is being embedded in an expert system. The background, design and status of both projects are described.

Heggestad, Harold M.↗
NASA NTRS2008

Pratt and Whitney Overview and Advanced Health Management Program

Hardware Development Activity: Design and Test Custom Multi-layer Circuit Boards for use in the Fault Emulation Unit; Logic design performed using VHDL; Layout power system for lab hardware; Work lab issues with software developers and software testers; Interface with Engine Systems personnel with performance of Engine hardware components; Perform off nominal testing with new engine hardware.

Inabinett, Calvin↗
DOE OSTI2024

Solid state protective smart plug device

A wireless-controlled smart plug device and methods of use and operation, using a solid state switch to provide electrical power from an outlet to a load, and provide protection against overload, short circuit, ground, arc, or voltage surge faults. The switch includes a bidirectional semiconductor switch with two back-to-back connected transistors, such as silicon power MOSFETs, silicon insulated-gate bipolar transistors (IGBTs), silicon carbide (SiC) transistors, or gallium nitride (GaN) transistors, each configured to control the current flow from the electrical receptacle to the external electrical load.

Shen, Zheng↗
DOE OSTI2025

Logical error rates for the surface code under a mixed coherent and stochastic circuit-level noise model inspired by trapped ions

With fault-tolerant quantum computing (FTQC) on the horizon, it is critical to understand sources of logical errors in plausible hardware implementations of quantum error-correcting codes. Detailed error modeling of computational instructions on particular FTQC architectures will enable the better prediction of error propagation in FT-encoded quantum circuits while revealing where greater attention is needed in hardware design. In this work, we consider logical error rates for the surface code implemented on a hypothetical grid-based trapped-ion quantum charge-coupled device architecture. Specifically, we construct logical channels for the idling surface code and examine its diamond error under a mixed coherent and stochastic circuit-level noise model inspired by trapped ions. We include the coherent dephasing noise that is known to accumulate during physical qubit idling and transport in these systems, determining idling and transport durations using the time-resolved output of an open-source trapped-ion surface code compiler. To estimate expectation values of logical Pauli observables following hardware circuits containing non-Clifford sources of noise, we utilize a Monte Carlo technique to sample from an underlying quasiprobability distribution of Clifford circuits that we independently simulate in a phase-sensitive fashion. We verify error suppression up to code distance 𝑑 = 11 at coherent dephasing rates near and below those of current-generation trapped-ion quantum computers and find that logical error rates align with those of analogous fully stochastic simulations in this regime. Exploring higher dephasing rates at 𝑑 = 3−5, we find evidence for growing coherent rotations about all three logical Pauli axes, increased diagonal logical error process matrix elements relative to those of stochastic simulations, and a reduced dephasing rate threshold. Overall, our work paves a way toward realistic hardware emulation of small fault-tolerant quantum processes, e.g., members of an FTQC instruction set.

Quantum benchmarking↗
NASA NTRS2015

Software Testbed for Developing and Evaluating Integrated Autonomous Subsystems

To implement fault tolerant autonomy in future space systems, it will be necessary to integrate planning, adaptive control, and state estimation subsystems. However, integrating these subsystems is difficult, time-consuming, and error-prone. This paper describes Intelliface/ADAPT, a software testbed that helps researchers develop and test alternative strategies for integrating planning, execution, and diagnosis subsystems more quickly and easily. The testbed's architecture, graphical data displays, and implementations of the integrated subsystems support easy plug and play of alternate components to support research and development in fault-tolerant control of autonomous vehicles and operations support systems. Intelliface/ADAPT controls NASA's Advanced Diagnostics and Prognostics Testbed (ADAPT), which comprises batteries, electrical loads (fans, pumps, and lights), relays, circuit breakers, invertors, and sensors. During plan execution, an experimentor can inject faults into the ADAPT testbed by tripping circuit breakers, changing fan speed settings, and closing valves to restrict fluid flow. The diagnostic subsystem, based on NASA's Hybrid Diagnosis Engine (HyDE), detects and isolates these faults to determine the new state of the plant, ADAPT. Intelliface/ADAPT then updates its model of the ADAPT system's resources and determines whether the current plan can be executed using the reduced resources. If not, the planning subsystem generates a new plan that reschedules tasks, reconfigures ADAPT, and reassigns the use of ADAPT resources as needed to work around the fault. The resource model, planning domain model, and planning goals are expressed using NASA's Action Notation Modeling Language (ANML). Parts of the ANML model are generated automatically, and other parts are constructed by hand using the Planning Model Integrated Development Environment, a visual Eclipse-based IDE that accelerates ANML model development. Because native ANML planners are currently under development and not yet sufficiently capable, the ANML model is translated into the New Domain Definition Language (NDDL) and sent to NASA's EUROPA planning system for plan generation. The adaptive controller executes the new plan, using augmented, hierarchical finite state machines to select and sequence actions based on the state of the ADAPT system. Real-time sensor data, commands, and plans are displayed in information-dense arrays of timelines and graphs that zoom and scroll in unison. A dynamic schematic display uses color to show the real-time fault state and utilization of the system components and resources. An execution manager coordinates the activities of the other subsystems. The subsystems are integrated using the Internet Communications Engine (ICE). an object-oriented toolkit for building distributed applications.

Testbed↗