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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 181 records · Page 10
All sourcesNASA NTRSDOE OSTI
NASA NTRS1987

High data rate Reed-Solomon encoding and decoding using VLSI technology

Presented as an implementation of a Reed-Solomon encode and decoder, which is 16-symbol error correcting, each symbol is 8 bits. This Reed-Solomon (RS) code is an efficient error correcting code that the National Aeronautics and Space Administration (NASA) will use in future space communications missions. A Very Large Scale Integration (VLSI) implementation of the encoder and decoder accepts data rates up 80 Mbps. A total of seven chips are needed for the decoder (four of the seven decoding chips are customized using 3-micron Complementary Metal Oxide Semiconduction (CMOS) technology) and one chip is required for the encoder. The decoder operates with the symbol clock being the system clock for the chip set. Approximately 1.65 billion Galois Field (GF) operations per second are achieved with the decoder chip set and 640 MOPS are achieved with the encoder chip.

Miller, Warner↗
NASA NTRS2003

Cascade Back-Propagation Learning in Neural Networks

The cascade back-propagation (CBP) algorithm is the basis of a conceptual design for accelerating learning in artificial neural networks. The neural networks would be implemented as analog very-large-scale integrated (VLSI) circuits, and circuits to implement the CBP algorithm would be fabricated on the same VLSI circuit chips with the neural networks. Heretofore, artificial neural networks have learned slowly because it has been necessary to train them via software, for lack of a good on-chip learning technique. The CBP algorithm is an on-chip technique that provides for continuous learning in real time. Artificial neural networks are trained by example: A network is presented with training inputs for which the correct outputs are known, and the algorithm strives to adjust the weights of synaptic connections in the network to make the actual outputs approach the correct outputs. The input data are generally divided into three parts. Two of the parts, called the "training" and "cross-validation" sets, respectively, must be such that the corresponding input/output pairs are known. During training, the cross-validation set enables verification of the status of the input-to-output transformation learned by the network to avoid over-learning. The third part of the data, termed the "test" set, consists of the inputs that are required to be transformed into outputs; this set may or may not include the training set and/or the cross-validation set. Proposed neural-network circuitry for on-chip learning would be divided into two distinct networks; one for training and one for validation. Both networks would share the same synaptic weights.

Duong, Tuan A.↗
NASA NTRS1990

GaAs VLSI for aerospace electronics

Advanced aerospace electronics systems require high-speed, low-power, radiation-hard, digital components for signal processing, control, and communication applications. GaAs VLSI devices provide a number of advantages over silicon devices including higher carrier velocities, ability to integrate with high performance optical devices, and high-resistivity substrates that provide very short gate delays, good isolation, and tolerance to many forms of radiation. However, III-V technologies also have disadvantages, such as lower yield compared to silicon MOS technology. Achieving very large scale integration (VLSI) is particularly important for fast complex systems. At very short gate delays (less than 100 ps), chip-to-chip interconnects severely degrade circuit clock rates. Complex systems, therefore, benefit greatly when as many gates as possible are placed on a single chip. To fully exploit the advantages of GaAs circuits, attention must be focused on achieving high integration levels by reducing power dissipation, reducing the number of devices per logic function, and providing circuit designs that are more tolerant to process and environmental variations. In addition, adequate noise margin must be maintained to ensure a practical yield.

Larue, G.↗
NASA NTRS1993

Particle-Gas Dynamics in the Midplane of a Protoplanetary Nebula

In this paper, we study the stage of planetary formation during which the particulate material is still dispersed as centimeter-to-meter sized primordial aggregates. During this stage, particles are able to settle toward the midplane into a layer of mass density comparable to or much greater than that of the gas. Nonlinear, coupled interactions between the particles and the nebula gas become significant and ultimately determine the vertical profiles of the particle density and the mean velocities of the particles and the nearby gas. This is the environment in which the earliest planetesimals probably form. Our numerical models rely on the Reynolds averaged Navier-Stokes equations for the gas and particles and are fully viscous and turbulent (and, for the particles. compressible). Our turbulence modeling uses a Prandtl local shear parametrization, validated by laboratory experiments. We have developed a new model for particle diffusion involving the profile of the nebula gas turbulence and the particle Schmidt number, which is a function of particle size and density. We model a cool, quiescent nebula at 1 AU (280 K) and 10 AU (90 K) and a higher temperature stage (1000 K) at 1 AU. Our main results include: (a) rapid accretion of planetesimals by gravitationally unstable fragmentation on an orbital time scale (the 'Goldreich-Ward instability') is unlikely to occur until objects have already accreted by some other process to the mass of the largest known meteorite samples, if at all; (b) from 'seeds' as small as 10 m, growth of 10- to 100-km planetesimals can proceed rapidly by drift-augmented accretion in the particle-rich midplane with orbital decay of about 1% for the growing planetesimals; (c) outward transport of vapor and small entrained chips can account for significant radial compositional and mineralogical mixing in primitive meteorite parent bodies. Other implications may be drawn concerning particle random collisional velocities and the time scales of midplane turbulence.

Cuzzi, Jeffrey N.↗
NASA NTRS2015

Embedded Thermal Control for Subsystems for Next Generation Spacecraft Applications

Thermal Fluids and Analysis Workshop, Silver Spring MD NCTS 21070-15. NASA, the Defense Department and commercial interests are actively engaged in developing miniaturized spacecraft systems and scientific instruments to leverage smaller cheaper spacecraft form factors such as CubeSats. This paper outlines research and development efforts among Goddard Space Flight Center personnel and its several partners to develop innovative embedded thermal control subsystems. Embedded thermal control subsystems is a cross cutting enabling technology integrating advanced manufacturing techniques to develop multifunctional intelligent structures to reduce Size, Weight and Power (SWaP) consumption of both the thermal control subsystem and overall spacecraft. Embedded thermal control subsystems permit heat acquisition and rejection at higher temperatures than state of the art systems by employing both advanced heat transfer equipment (integrated heat exchangers) and high heat transfer phenomena. The Goddard Space Flight Center Thermal Engineering Branch has active investigations seeking to characterize advanced thermal control systems for near term spacecraft missions. The embedded thermal control subsystem development effort consists of fundamental research as well as development of breadboard and prototype hardware and spaceflight validation efforts. This paper will outline relevant fundamental investigations of micro-scale heat transfer and electrically driven liquid film boiling. The hardware development efforts focus upon silicon based high heat flux applications (electronic chips, power electronics etc.) and multifunctional structures. Flight validation efforts include variable gravity campaigns and a proposed CubeSat based flight demonstration of a breadboard embedded thermal control system. The CubeSat investigation is technology demonstration will characterize in long-term low earth orbit a breadboard embedded thermal subsystem and its individual components to develop optimized operational schema.

Spacecraft Systems↗
NASA NTRS2024

Superfluid-Tight Cryogenic Receiver With Continuous Sub-Kelvin Cooling for EXCLAIM

The EXperiment for Cryogenic Large-Aperture Intensity Mapping (EXCLAIM) is a balloon-borne telescope designed to survey star formation over cosmological time scales using intensity mapping in the 420 – 540 GHz frequency range. EXCLAIM uses a fully cryogenic telescope coupled to six on-chip spectrometers featuring kinetic inductance detectors (KIDs) to achieve high sensitivity, allowing for fast integration in dark atmospheric windows. The telescope receiver is cooled to ≈ 1.7 K by immersion in a superfluid helium bath and enclosed in a superfluid-tight shell with a meta-material anti-reflection coated silicon window. In addition to the optics and the spectrometer package, the receiver contains the magnetic shielding, the cryogenic segment of the spectrometer readout, and the sub-Kelvin cooling system. A three-stage continuous adiabatic demagnetization refrigerator (CADR) keeps the detectors at 100 mK while a 4He sorption cooler provides a 900 mK thermal intercept for mechanical suspensions and coaxial cables. We present the design of the EXCLAIM receiver and report on the flight-like testing of major receiver components, including the superfluid-tight receiver window and the sub-Kelvin coolers.

continuous adiabatic demagnetization refrigerator↗
NASA NTRS1985

The 1.2 micron CMOS technology

A set of test structures was designed using the Jet Propulsion Laboratory (JPL) test chip assembler and was used to evaluate the first CMOS-bulk foundry runs with feature sizes of 1.2 microns. In addition to the problems associated with the physical scaling of the structures, this geometry provided an additional set of problems, since the design files had to be generated in such a way as to be capable of being processed through p-well, n-well, and twin-well processing lines. This requirement meant that the files containing the geometric design rules as well as the structure design files had to produce process-insensitive designs, a requirement that does not apply to the more mature 3.0-micron CMOS feature size technology. Because of the photolithographic steps required with this feature size, the maximum allowable chip size was 10 x 10 mm, and this chip was divided into 24 project areas, with each area being 1.6 x 1.6 mm in size. The JPL-designed structures occupied 13 out of the 21 allowable project sizes and provided the only test information obtained from these three preliminary runs. The structures were used to successfully evaluate three different manufacturing runs through two separate foundries.

Pina, C. A.↗
NASA NTRS1998

Computational Modeling of Semiconductor Dynamics at Femtosecond Time Scales

The Interchange No. NCC2-5149 deals with the emerging technology of photonic (or optoelectronic) integrated circuits (PICs or OEICs). In PICs, optical and electronic components are grown together on the same chip. To build such devices and subsystems, one needs to model the entire chip. PICs are useful for building components for integrated optical transmitters, integrated optical receivers, optical data storage systems, optical interconnects, and optical computers. For example, the current commercial rate for optical data transmission is 2.5 gigabits per second, whereas the use of shorter pulses to improve optical transmission rates would yield an increase of 400 to 1000 times. The improved optical data transmitters would be used in telecommunications networks and computer local-area networks. Also, these components can be applied to activities in space, such as satellite to satellite communications, when the data transmissions are made at optical frequencies. The research project consisted of developing accurate computer modeling of electromagnetic wave propagation in semiconductors. Such modeling is necessary for the successful development of PICs. More specifically, these computer codes would enable the modeling of such devices, including their subsystems, such as semiconductor lasers and semiconductor amplifiers in which there is femtosecond pulse propagation. Presently, there are no computer codes that could provide this modeling. Current codes do not solve the full vector, nonlinear, Maxwell's equations, which are required for these short pulses and also current codes do not solve the semiconductor Bloch equations, which are required to accurately describe the material's interaction with femtosecond pulses. The research performed under NCC2-5149 solves the combined Maxwell's and Bloch's equations.

Agrawal, Govind P.↗
NASA NTRS1991

Non-volatile, high density, high speed, Micromagnet-Hall effect Random Access Memory (MHRAM)

The micromagnetic Hall effect random access memory (MHRAM) has the potential of replacing ROMs, EPROMs, EEPROMs, and SRAMs because of its ability to achieve non-volatility, radiation hardness, high density, and fast access times, simultaneously. Information is stored magnetically in small magnetic elements (micromagnets), allowing unlimited data retention time, unlimited numbers of rewrite cycles, and inherent radiation hardness and SEU immunity, making the MHRAM suitable for ground based as well as spaceflight applications. The MHRAM device design is not affected by areal property fluctuations in the micromagnet, so high operating margins and high yield can be achieved in large scale integrated circuit (IC) fabrication. The MHRAM has short access times (less than 100 nsec). Write access time is short because on-chip transistors are used to gate current quickly, and magnetization reversal in the micromagnet can occur in a matter of a few nanoseconds. Read access time is short because the high electron mobility sensor (InAs or InSb) produces a large signal voltage in response to the fringing magnetic field from the micromagnet. High storage density is achieved since a unit cell consists only of two transistors and one micromagnet Hall effect element. By comparison, a DRAM unit cell has one transistor and one capacitor, and a SRAM unit cell has six transistors.

Wu, Jiin C.↗
NASA NTRS1992

The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element

A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.

Deyong, Mark R.↗
NASA NTRS1995

Biomorphic architectures for autonomous Nanosat designs

Modern space tool design is the science of making a machine both massively complex while at the same time extremely robust and dependable. We propose a novel nonlinear control technique that produces capable, self-organizing, micron-scale space machines at low cost and in large numbers by parallel silicon assembly. Experiments using biomorphic architectures (with ideal space attributes) have produced a wide spectrum of survival-oriented machines that are reliably domesticated for work applications in specific environments. In particular, several one-chip satellite prototypes show interesting control properties that can be turned into numerous application-specific machines for autonomous, disposable space tasks. We believe that the real power of these architectures lies in their potential to self-assemble into larger, robust, loosely coupled structures. Assembly takes place at hierarchical space scales, with different attendant properties, allowing for inexpensive solutions to many daunting work tasks. The nature of biomorphic control, design, engineering options, and applications are discussed.

Hasslacher, Brosl↗
NASA NTRS1993

Implementation and Performance of GaAs Digital Signal Processing ASICs

The feasibility of performing high speed digital signal processing in GaAs gate array technology has been demonstrated with the successful implementation of a VLSI communications chip set for NASA's Deep Space Network. This paper describes the techniques developed to solve some of the technology and implementation problems associated with large scale integration of GaAs gate arrays.

Whitaker, William D.↗
NASA NTRS2005

Automated Image Registration Using Morphological Region of Interest Feature Extraction

With the recent explosion in the amount of remotely sensed imagery and the corresponding interest in temporal change detection and modeling, image registration has become increasingly important as a necessary first step in the integration of multi-temporal and multi-sensor data for applications such as the analysis of seasonal and annual global climate changes, as well as land use/cover changes. The task of image registration can be divided into two major components: (1) the extraction of control points or features from images; and (2) the search among the extracted features for the matching pairs that represent the same feature in the images to be matched. Manual control feature extraction can be subjective and extremely time consuming, and often results in few usable points. Automated feature extraction is a solution to this problem, where desired target features are invariant, and represent evenly distributed landmarks such as edges, corners and line intersections. In this paper, we develop a novel automated registration approach based on the following steps. First, a mathematical morphology (MM)-based method is used to obtain a scale-orientation morphological profile at each image pixel. Next, a spectral dissimilarity metric such as the spectral information divergence is applied for automated extraction of landmark chips, followed by an initial approximate matching. This initial condition is then refined using a hierarchical robust feature matching (RFM) procedure. Experimental results reveal that the proposed registration technique offers a robust solution in the presence of seasonal changes and other interfering factors. Keywords-Automated image registration, multi-temporal imagery, mathematical morphology, robust feature matching.

Plaza, Antonio↗
NASA NTRSDate not supplied

Demonstration of How Manufacturing Innovations Challenge Conventional Structural Design

For almost 100 years, commercial aircraft have been fabricated using riveted aluminum alloy structures. Aside from refining aircraft designs for better aerodynamic efficiency, improving alloy compositions, and automating assembly steps, fuselage construction remains largely unchanged today. The intent of the lightweight metallic fuselage prototype undertaken in NASA’s Advanced Air Transport Technology project was to demonstrate innovative forming and joining processes that advance the design paradigm, i.e. achieve high-rate manufacturing and reduce assembly time/costs. Over the past decade, researchers at NASA Langley Research Center have evaluated the potential to modify the flow forming process to produce near-net shaped cylinders, integrally stiffened along the cylinder axis, for space launch vehicles. The production of integral stiffeners in a formed aluminum cylinder, the size of the Space Shuttle external tank, replaced machined thick plate and welding steps to eliminate > 500,000 pounds of machining chips and ~ 0.5 miles of welds. The flow forming method, called the Integrally Stiffened Cylinder (ISC) process, was successfully demonstrated up to the 10-foot diameter scale, which laid the groundwork for the current investigation of metallic fuselage structures. Using the ISC process as the basis for the re-design of a metallic fuselage eliminates hundreds of thousands of holes and rivets, while significantly reducing assembly time and crack initiation sites in the integral structure. However, the ISC process is not currently configured to fabricate circumferential ring frames for carrying fuselage internal pressure loads. Consequently, a trade study was performed to assess existing and advanced manufacturing processes, including additive manufacturing, forming, and welding. The approach with the lowest barriers to success, while simultaneously improving manufacturing time and cost, was to use formed ring frame segments attached to the ISC via Refill Friction Stir Spot Welding (RFSSW). The RFSSW process is five times faster than drilling, reaming, and riveting and provides similar mechanical performance. Finishing the fuselage structure with conventional windows, floor beams, and floor panels can then be accomplished using incumbent assembly methods, thereby maximizing reuse of existing infrastructure for aircraft construction. Structural analyses were performed to assess and optimize the geometric variables of integrated skin and stiffener configurations. A cost benefit and manufacturing rate analysis was also performed to compare against the current state-of-the-art for single aisle transport class aircraft. The resulting structure offers a weight reduction that rivals current graphite-epoxy composite fuselage structures. The projected manufacturing rate is close to double current metallic fuselages and six times faster than current composite manufacturing practices. The damage tolerance properties of a monocoque fuselage structure have yet to be assessed, but past integral airframe structural work has exploited geometric features to blunt or turn cracks. This concept offers promise that integrated structures can meet stringent aircraft durability specifications. An important benefit is that such aluminum fuselage structures may be inspected and repaired using established practices and existing expertise. Finally, pursuit of advanced manufacturing processes for future aluminum fuselages minimizes waste and the structure is 100% recyclable at the end-of-life for maximum sustainability.

aluminum↗
NASA NTRS2009

Advanced Embedded Active Assemblies for Extreme Space Applications

This work describes the development and evaluation of advanced technologies for the integration of electronic die within membrane polymers. Specifically, investigators thinned silicon die, electrically connecting them with circuits on flexible liquid crystal polymer (LCP), using gold thermo-compression flip chip bonding, and embedding them within the material. Daisy chain LCP assemblies were thermal cycled from -135 to +85degC (Mars surface conditions for motor control electronics). The LCP assembly method was further utilized to embed an operational amplifier designed for operation within the Mars surface ambient. The embedded op-amp assembly was evaluated with respect to the influence of temperature on the operational characteristics of the device. Applications for this technology range from multifunctional, large area, flexible membrane structures to small-scale, flexible circuits that can be fit into tight spaces for flex to fit applications.

lead bonding↗
NASA NTRS1985

Nuclear Science Symposium, 31st and Symposium on Nuclear Power Systems, 16th, Orlando, FL, October 31-November 2, 1984, Proceedings

Topics related to physics instrumentation are discussed, taking into account cryostat and electronic development associated with multidetector spectrometer systems, the influence of materials and counting-rate effects on He-3 neutron spectrometry, a data acquisition system for time-resolved muscle experiments, and a sensitive null detector for precise measurements of integral linearity. Other subjects explored are concerned with space instrumentation, computer applications, detectors, instrumentation for high energy physics, instrumentation for nuclear medicine, environmental monitoring and health physics instrumentation, nuclear safeguards and reactor instrumentation, and a 1984 symposium on nuclear power systems. Attention is given to the application of multiprocessors to scientific problems, a large-scale computer facility for computational aerodynamics, a single-board 32-bit computer for the Fastbus, the integration of detector arrays and readout electronics on a single chip, and three-dimensional Monte Carlo simulation of the electron avalanche in a proportional counter.

Biggerstaff, J. A.↗
NASA NTRS1986

Digital transmitter - Simple, yet precise

A transmitter developed for operation at high digital transmission speeds is described. It is a complex system that produces a clean waveform with data rates as high as 1 Mb/s; and its design makes it possible to vary all possible modulation schemes by reprogramming a chip, to vary data-transmission rates with the clock frequency, and to shape pulses without distortion. The design, furthermore, can be adapted to very-large-scale-integration (VLSI) fabrication and mass production. A prototype QPSK residual carrier modulation transmitter was fabricated and tested. The purpose was to create a deep null in the data spectrum to transmit a tone or residual carrier along with the modulation.

Davarian, F.↗