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All sourcesNASA NTRSDOE OSTI
NASA NTRS2009

Large-Aperture Membrane Active Phased-Array Antennas

Large-aperture phased-array microwave antennas supported by membranes are being developed for use in spaceborne interferometric synthetic aperture radar systems. There may also be terrestrial uses for such antennas supported on stationary membranes, large balloons, and blimps. These antennas are expected to have areal mass densities of about 2 kg/sq m, satisfying a need for lightweight alternatives to conventional rigid phased-array antennas, which have typical areal mass densities between 8 and 15 kg/sq m. The differences in areal mass densities translate to substantial differences in total mass in contemplated applications involving aperture areas as large as 400 sq m. A membrane phased-array antenna includes patch antenna elements in a repeating pattern. All previously reported membrane antennas were passive antennas; this is the first active membrane antenna that includes transmitting/receiving (T/R) electronic circuits as integral parts. Other integral parts of the antenna include a network of radio-frequency (RF) feed lines (more specifically, a corporate feed network) and of bias and control lines, all in the form of flexible copper strip conductors on flexible polymeric membranes. Each unit cell of a prototype antenna (see Figure 1) contains a patch antenna element and a compact T/R module that is compatible with flexible membrane circuitry. There are two membrane layers separated by a 12.7-mm air gap. Each membrane layer is made from a commercially available flexible circuit material that, as supplied, comprises a 127-micron-thick polyimide dielectric layer clad on both sides with 17.5-micron-thick copper layers. The copper layers are patterned into RF, bias, and control conductors. The T/R module is located on the back side of the ground plane and is RF-coupled to the patch element via a slot. The T/R module is a hybrid multilayer module assembled and packaged independently and attached to the membrane array. At the time of reporting the information for this article, an 8 16 passive array (not including T/R modules) and a 2 4 active array (including T/R modules) had been demonstrated, and it was planned to fabricate and test larger arrays.

Karasik, Boris↗
NASA NTRSDate not supplied

Progress Towards SiC ASICs for Extreme Temperature and Radiation Environments

This presentation describes development and demonstrations of semiconductor integrated circuits (ICs) and ceramic packaging that are arguably the most environmentally durable transistor electronics ever demonstrated. Silicon carbide (SiC) junction field effect transistor-resistor (JFET-R) ICs fabricated by NASA Glenn Research Center with two-level interconnect have successfully operated for over 1 year in 500 °C air-ambient, 60 days in 460 °C and 9.3 MPa pressure caustic Venus surface environment test chamber, and radiation exposure through 7 Mrad(Si) total ionizing dose (TID) and 86 MeV-cm2/mg heavy ion strikes. Furthermore, these ICs have also demonstrated operation from -190 °C to +812 °C (over 1000 °C temperature span) without significant change in signal (input /output) or power supply voltages. While the operating frequency and functional complexity is far below silicon-based ICs, these SiC application specific ICs (ASICs) are nevertheless becoming capable of providing unique and advantageous harsh-environment circuit functionality without cooling/sheltering overhead. With modest adjustments, the SiC JFET-R fabrication process is compatible with semiconductor mass-production tools and materials. As an initial step towards manufacture, a majority of processing steps to realize the next SiC JFET-R IC prototype wafer run have been outsourced to commercial foundry. It is expected that further upscaling combined with technology transfer to commercial production will lower investment and risk barriers to useful application deployment.

high temperature↗
NASA NTRS1987

Advanced Components for Spaceborne Infrared Astronomy

Basic improvements in the technology of low noise read-out systems for low background detectors were demonstrated. Using discrete JFET integrating amplifiers at their optimum temperature of 55 K, read noise less than 7.5 electrons in 128 seconds of integration was obtained. Two models of single channel integrators are now available, the JF-77 for use between 50 and 80 K and the JF-4 for lower temperatures. A 1 x 15 linear array of complete integrators on a single integrated circuit was developed and will be made available in the near future. The successful operation of a superconducting stepper motor was demonstrated. The motor shows a three fold increase in torque over conventional motors operating at room temperature. The success of the motor stems from the use of superconducting coils in conjunction with developments in bearings for cryogenic use, rare-earth rotors, and motor cooling techniques. The current state of development will allow the rapid development of motors optimized for specific applications. An electronic switch capable of resetting cooled JFET integrating amplifiers was developed. The JFET integrating amplifiers that use this switch have demonstrated read noise of less than 10 electrons. The JFET reset device exhibits an extremely high open impedance and low leakage current. Capacitance is sufficiently low so as not to impair amplifier sensitivity. The effects of transient switching charges are minimized by a compensation technique and variable transient current problems inherent to devices of this type are overcome by external circuity.

Davidson, Arnold W.↗
NASA NTRS1997

A Novel Silicon Micromachined Integrated MCM Thermal Management System

"Micromachining" is a chemical means of etching three-dimensional structures, typically in single- crystalline silicon. These techniques are leading toward what is coming to be referred to as MEMS (Micro Electro Mechanical Systems), where in addition to the ordinary two-dimensional (planar) microelectronics, it is possible to build three-dimensional n-ticromotors, electrically- actuated raicrovalves, hydraulic systems and much more on the same microchip. These techniques become possible because of differential etching rates of various crystallographic planes and materials used for semiconductor n-ticrofabfication. The University of Cincinnati group in collaboration with Karl Baker at NASA Lewis were the first to form micro heat pipes in silicon by the above techniques. Current work now in progress using MEMS technology is now directed towards the development of the next generation in MCM (Multi Chip Module) packaging. Here we propose to develop a complete electronic thermal management system which will allow densifica6on in chip stacking by perhaps two orders of magnitude. Furthermore the proposed technique will allow ordinary conu-nercial integrated chips to be utilized. Basically, the new technique involves etching square holes into a silicon substrate and then inserting and bonding commercially available integrated chips into these holes. For example, over a 100 1/4 in. by 1 /4 in. integrated chips can be placed on a 4 in. by 4 in. silicon substrate to form a Multi-Chip Module (MCM). Placing these MCM's in-line within an integrated rack then allows for three-diniensional stacking. Increased miniaturization of microelectronic circuits will lead to very high local heat fluxes. A high performance thermal management system will be specifically designed to remove the generated energy. More specifically, a compact heat exchanger with milli / microchannels will be developed and tested to remove the heat through the back side of this MCM assembly for moderate and high heat flux applications, respectively. The high heat load application of particular interest in mind is the motor controller developed by Martin Marietta for Nasa to control the thruster's directional actuators on space vechicles. Work is also proposed to develop highly advanced and improved porous wick structures for use in advanced heat loops. The porous wick will be micromachined from silicon using MEMS technology, thus permitting far superior control of pore size and pore distribution (over wicks made from sintered n-ietals), which in turn is expected to led to significantly improved heat loop performance.

Kazmierczak, M. J.↗
NASA NTRS1993

Total Ionizing Dose Effects in 12-Bit Successive-Approximation Analog-To-Digital Converters

Analog-to-digital (A/D) converters are critical components in many space and military systems, and there have been numerous advances in A/D converter technology that have increased the resolution and conversion time. The increased performance is due to two factors: (1) advances in circuit design and complexity, which have increased the number of components and the integration density; and (2) new process technologies, such as BiCMOS, which provide better performance, cost, and smaller size in mixed-signal circuits. High-speed A/D converters, with conversion rates above 1 MHz, present a challenge to circuit designers and test engineers. Their complex architectures and high-performance specifications result in numerous possible failure modes when they are subjected to ionizing radiation. The dominant failure mode may depend on the specific application because the fundamental effects on MOS and bipolar transistors are strongly affected by bias conditions.

Lee, C. I.↗
NASA NTRS1995

Monolithically interconnected GaAs solar cells: A new interconnection technology for high voltage solar cell output

Photovoltaic linear concentrator arrays can benefit from high performance solar cell technologies being developed at AstroPower. Specifically, these are the integration of thin GaAs solar cell and epitaxial lateral overgrowth technologies with the application of monolithically interconnected solar cell (MISC) techniques. This MISC array has several advantages which make it ideal for space concentrator systems. These are high system voltage, reliable low cost monolithically formed interconnections, design flexibility, costs that are independent of array voltage, and low power loss from shorts, opens, and impact damage. This concentrator solar cell will incorporate the benefits of light trapping by growing the device active layers over a low-cost, simple, PECVD deposited silicon/silicon dioxide Bragg reflector. The high voltage-low current output results in minimal 12R losses while properly designing the device allows for minimal shading and resistance losses. It is possible to obtain open circuit voltages as high as 67 volts/cm of solar cell length with existing technology. The projected power density for the high performance device is 5 kW/m for an AMO efficiency of 26% at 1 5X. Concentrator solar cell arrays are necessary to meet the power requirements of specific mission platforms and can supply high voltage power for electric propulsion systems. It is anticipated that the high efficiency, GaAs monolithically interconnected linear concentrator solar cell array will enjoy widespread application for space based solar power needs. Additional applications include remote man-portable or ultra-light unmanned air vehicle (UAV) power supplies where high power per area, high radiation hardness and a high bus voltage or low bus current are important. The monolithic approach has a number of inherent advantages, including reduced cost per interconnect and increased reliability of array connections. There is also a high potential for a large number of consumer products. Dual-use applications can include battery chargers and remote power supplies for consumer electronics products such as portable telephones/beepers, portable radios, CD players, dashboard radar detectors, remote walkway lighting, etc.

Dinetta, L. C.↗
NASA NTRS1994

Parallel digital modem using multirate digital filter banks

A new class of architectures for an all-digital modem is presented in this report. This architecture, referred to as the parallel receiver (PRX), is based on employing multirate digital filter banks (DFB's) to demodulate, track, and detect the received symbol stream. The resulting architecture is derived, and specifications are outlined for designing the DFB for the PRX. The key feature of this approach is a lower processing rate then either the Nyquist rate or the symbol rate, without any degradation in the symbol error rate. Due to the freedom in choosing the processing rate, the designer is able to arbitrarily select and use digital components, independent of the speed of the integrated circuit technology. PRX architecture is particularly suited for high data rate applications, and due to the modular structure of the parallel signal path, expansion to even higher data rates is accommodated with each. Applications of the PRX would include gigabit satellite channels, multiple spacecraft, optical links, interactive cable-TV, telemedicine, code division multiple access (CDMA) communications, and others.

Sadr, Ramin↗
NASA NTRS1983

Rotorcraft air transportation

Intermodal relationships and the particular ways in which they affect public transportation applications of rotorcraft are addressed. Some aspects of integrated services and general comparisons with other transportation modes are reviewed. Two potential application scenarios are discussed: down-to-downtown rotorcraft service and urban public transport rotorcraft service. It is concluded that to integrate well with ground access modes community rotorcraft service should be limited stop service with published schedules, and operate on a few specific routes between a few specific destinations. For downtown-to-downtown service, time savings favorable to rotorcraft are benefits that reflect its more direct access, relatively higher line-haul travel speeds, and less circuitous travel. For the scenario of public transport within urban areas, first, improving cruise speeds has a limited potential due to allowing for a ""station spacing'' effect. Secondly, public acceptance of higher acceleration/deceleration rates may be just as effective as a technological innovation as achieving higher cruise speeds.

Gilbert, G. A.↗
NASA NTRS2000

Highly Parallel Computing Architectures by using Arrays of Quantum-dot Cellular Automata (QCA): Opportunities, Challenges, and Recent Results

There has been significant improvement in the performance of VLSI devices, in terms of size, power consumption, and speed, in recent years and this trend may also continue for some near future. However, it is a well known fact that there are major obstacles, i.e., physical limitation of feature size reduction and ever increasing cost of foundry, that would prevent the long term continuation of this trend. This has motivated the exploration of some fundamentally new technologies that are not dependent on the conventional feature size approach. Such technologies are expected to enable scaling to continue to the ultimate level, i.e., molecular and atomistic size. Quantum computing, quantum dot-based computing, DNA based computing, biologically inspired computing, etc., are examples of such new technologies. In particular, quantum-dots based computing by using Quantum-dot Cellular Automata (QCA) has recently been intensely investigated as a promising new technology capable of offering significant improvement over conventional VLSI in terms of reduction of feature size (and hence increase in integration level), reduction of power consumption, and increase of switching speed. Quantum dot-based computing and memory in general and QCA specifically, are intriguing to NASA due to their high packing density (10(exp 11) - 10(exp 12) per square cm ) and low power consumption (no transfer of current) and potentially higher radiation tolerant. Under Revolutionary Computing Technology (RTC) Program at the NASA/JPL Center for Integrated Space Microelectronics (CISM), we have been investigating the potential applications of QCA for the space program. To this end, exploiting the intrinsic features of QCA, we have designed novel QCA-based circuits for co-planner (i.e., single layer) and compact implementation of a class of data permutation matrices, a class of interconnection networks, and a bit-serial processor. Building upon these circuits, we have developed novel algorithms and QCA-based architectures for highly parallel and systolic computation of signal/image processing applications, such as FFT and Wavelet and Wlash-Hadamard Transforms.

Fijany, Amir↗
NASA NTRS2010

Compact Rare Earth Emitter Hollow Cathode

A compact, high-current, hollow cathode utilizing a lanthanum hexaboride (LaB6) thermionic electron emitter has been developed for use with high-power Hall thrusters and ion thrusters. LaB6 cathodes are being investigated due to their long life, high current capabilities, and less stringent xenon purity and handling requirements compared to conventional barium oxide (BaO) dispenser cathodes. The new cathode features a much smaller diameter than previously developed versions that permit it to be mounted on axis of a Hall thruster ( internally mounted ), as opposed to the conventional side-mount position external to the outer magnetic circuit ("externally mounted"). The cathode has also been reconfigured to be capable of surviving vibrational loads during launch and is designed to solve the significant heater and materials compatibility problems associated with the use of this emitter material. This has been accomplished in a compact design with the capability of high-emission current (10 to 60 A). The compact, high-current design has a keeper diameter that allows the cathode to be mounted on the centerline of a 6- kW Hall thruster, inside the iron core of the inner electromagnetic coil. Although designed for electric propulsion thrusters in spacecraft station- keeping, orbit transfer, and interplanetary applications, the LaB6 cathodes are applicable to the plasma processing industry in applications such as optical coatings and semiconductor processing where reactive gases are used. Where current electrical propulsion thrusters with BaO emitters have limited life and need extremely clean propellant feed systems at a significant cost, these LaB6 cathodes can run on the crudest-grade xenon propellant available without impact. Moreover, in a laboratory environment, LaB6 cathodes reduce testing costs because they do not require extended conditioning periods under hard vacuum. Alternative rare earth emitters, such as cerium hexaboride (CeB6) can be used in this configuration with possibly an even longer emitter life. This cathode is specifically designed to integrate on the centerline of a high-power Hall thruster, thus eliminating the asymmetries in the plasma discharge common to cathodes previously mounted externally to the thruster s magnetic circuit. An alternative configuration for the cathode uses an external propellant feed. This diverts a fraction of the total cathode flow to an external feed, which can improve the cathode coupling efficiency at lower total mass flow rates. This can improve the overall thruster efficiency, thereby decreasing the required propellant loads for different missions. Depending on the particular mission, reductions in propellant loads can lead to mission enabling capabilities by allowing launch vehicle step-down, greater payload capability, or by extending the life of a spacecraft.

Watkins, Ronald↗
NASA NTRS1980

Application of software technology to a future spacecraft computer design

A study was conducted to determine how major improvements in spacecraft computer systems can be obtained from recent advances in hardware and software technology. Investigations into integrated circuit technology indicated that the CMOS/SOS chip set being developed for the Air Force Avionics Laboratory at Wright Patterson had the best potential for improving the performance of spaceborne computer systems. An integral part of the chip set is the bit slice arithmetic and logic unit. The flexibility allowed by microprogramming, combined with the software investigations, led to the specification of a baseline architecture and instruction set.

Labaugh, R. J.↗
NASA NTRS1989

SEU In An Advanced Bipolar Integrated Circuit

Report summarizes investigation of single-event upsets (SEU) in bipolar integrated-circuit set of flip-flops (memory cells). Device tested made by advanced digital bipolar silicon process of Honeywell, Inc. Circuit chip contained 4 cells. Construction enabled study of effect of size on SEU behavior. Each cell externally biased so effect of bias current on SEU behavior. Results of study provides important information for optimal design of devices fabricated using buried-layer bipolar process operating in heavy-ion SEU environments. Designers use information to provide required levels of suppression of SEU in specific applications via combinations of size and/or cell-current scaling.

Zoutendyk, John A.↗
NASA NTRS1989

Electro-optic architecture for servicing sensors and actuators in advanced aircraft propulsion systems

A detailed design of a fiber optic propulsion control system, integrating favored sensors and electro-optics architecture is presented. Layouts, schematics, and sensor lists describe an advanced fighter engine system model. Components and attributes of candidate fiber optic sensors are identified, and evaluation criteria are used in a trade study resulting in favored sensors for each measurand. System architectural ground rules were applied to accomplish an electro-optics architecture for the favored sensors. A key result was a considerable reduction in signal conductors. Drawings, schematics, specifications, and printed circuit board layouts describe the detailed system design, including application of a planar optical waveguide interface.

Poppel, G. L.↗
NASA NTRS1992

The 10 kW power electronics for hydrogen arcjets

A combination of emerging mission considerations such as 'launch on schedule', resource limitations, and the development of higher power spacecraft busses has resulted in renewed interest in high power hydrogen arcjet systems with specific impulses greater than 1000 s for Earth-space orbit transfer and maneuver applications. Solar electric propulsion systems with about 10 kW of power appear to offer payload benefits at acceptable trip times. This work outlines the design and development of 10 kW hydrogen arcjet power electronics and results of arcjet integration testing. The power electronics incorporated a full bridge switching topology similar to that employed in state of the art 5 kW power electronics, and the output filter included an output current averaging inductor with an integral pulse generation winding for arcjet ignition. Phase shifted, pulse width modulation with current mode control was used to regulate the current delivered to arcjet, and a low inductance power stage minimized switching transients. Hybrid power Metal Oxide Semiconductor Field Effect Transistors were used to minimize conduction losses. Switching losses were minimized using a fast response, optically isolated, totem-pole gate drive circuit. The input bus voltage for the unit was 150 V, with a maximum output voltage of 225 V. The switching frequency of 20 kHz was a compromise between mass savings and higher efficiency. Power conversion efficiencies in excess of 0.94 were demonstrated, along with steady state load current regulation of 1 percent. The power electronics were successfully integrated with a 10 kW laboratory hydrogen arcjet, and reliable, nondestructive starts and transitions to steady state operation were demonstrated. The estimated specific mass for a flight packaged unit was 2 kg/kW.

Hamley, John A.↗
NASA NTRS1994

A programmable heater control circuit for spacecraft

Spacecraft thermal control is accomplished for many components through use of multilayer insulation systems, electrical heaters, and radiator systems. The heaters are commanded to maintain component temperatures within design specifications. The programmable heater control circuit (PHCC) was designed to obtain an effective and efficient means of spacecraft thermal control. The hybrid circuit provides use of control instrumentation as temperature data, available to the spacecraft central data system, reprogramming capability of the local microprocessor during the spacecraft's mission, and the elimination of significant spacecraft wiring. The hybrid integrated circuit has a temperature sensing and conditioning circuit, a microprocessor, and a heater power and control circuit. The device is miniature and housed in a volume which allows physical integration with the component to be controlled. Applications might include alternate battery-powered logic-circuit configurations. A prototype unit with appropriate physical and functional interfaces was procured for testing. The physical functionality and the feasibility of fabrication of the hybrid integrated circuit were successfully verified. The remaining work to develop a flight-qualified device includes fabrication and testing of a Mil-certified part. An option for completing the PHCC flight qualification testing is to enter into a joint venture with industry.

Nguyen, D. D.↗
NASA NTRS1982

Development and evaluation of integrated infrared arrays for astronomical applications

The status of a technology program to evaluate existing infrared detector arrays, and to develop improved ones for low background astronomical applications, is described. For applications such as the Shuttle Infrared Telescope Facility, arrays that cover as much of the 1-1000 micron range as possible are of interest. Low background test results for a 2 x 64 Si:Bi charge-injection-device, and 1 x 20 InSb charge-coupled-device arrays, are included. As a result of the present testing, improved, astronomy-optimized extrinsic silicon arrays in both linear and area formats are planned. Efforts to develop accumulation mode MOSFETs specifically for liquid helium temperatures, and cryogenic amplifier and multiplexer circuits, are discussed.

Mccreight, C. R.↗
NASA NTRS1993

A low-mass faraday cup experiment for the solar wind

Faraday cups have proven to be very reliable and accurate instruments capable of making 3-D velocity distribution measurements on spinning or 3-axis stabilized spacecraft. Faraday cup instrumentation continues to be appropriate for heliospheric missions. As an example, the reductions in mass possible relative to the solar wind detection system about to be flown on the WIND spacecraft were estimated. Through the use of technology developed or used at the MIT Center for Space Research but were not able to utilize for WIND: surface-mount packaging, field-programmable gate arrays, an optically-switched high voltage supply, and an integrated-circuit power converter, it was estimated that the mass of the Faraday Cup system could be reduced from 5 kg to 1.8 kg. Further redesign of the electronics incorporating hybrid integrated circuits as well as a decrease in the sensor size, with a corresponding increase in measurement cycle time, could lead to a significantly lower mass for other mission applications. Reduction in mass of the entire spacecraft-experiment system is critically dependent on early and continual collaborative efforts between the spacecraft engineers and the experimenters. Those efforts concern a range of issues from spacecraft structure to data systems to the spacecraft power voltage levels. Requirements for flight qualification affect use of newer, lighter electronics packaging and its implementation; the issue of quality assurance needs to be specifically addressed. Lower cost and reduced mass can best be achieved through the efforts of a relatively small group dedicated to the success of the mission. Such a group needs a fixed budget and greater control over quality assurance requirements, together with a reasonable oversight mechanism.

Lazarus, A. J.↗
NASA NTRS2013

Development of a 2K x 2K GaAs QWIP Focal Plane Array

We are developing the next generation of GaAs Quantum Well Infrared Photodetector (QWIP) focal plane arrays (FPAs) in preparation for future NASA space-borne Earth observing missions. It is anticipated that these missions will require both wider ground spatial coverage as well as higher ground imaging resolution. In order to demonstrate our capability in meeting these future goals we have taken a two-tiered approach in the next stage of advanced QWIP focal plane array development. We will describe our progress in the development of a 512 x 3,200 (512 x 3K) array format for this next generation thermal imaging array for the NASA Landsat project. However, there currently is no existing readout integrated circuit (ROIC) for this format array.so to demonstrate the ability to scale-up an existing ROIC we developed a 1,920 x 2,048 (2K x 2K) array and it hybridized to a Raytheon SB419 CTIA readout integrated circuit that was scaled up from their existing 512 x 640 SB339 ROIC. Two versions of the 512 x 3K QWIP array were fabricated to accommodate a future design scale-up of both the Indigo 9803 ROIC based on a 25 micron pixel dimension and a scale up of the Indigo 9705 ROIC based on a 30 micron pixel dimension. Neither readout for the 512 x 3K has yet to be developed but we have fabricated both versions of the array. We describe the design, development and test results of this effort as well as the specific applications these FPAs are intended to address.

Jhabvala, M.↗