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The development of SiC as a high temperature semiconductor material is discussed, focusing on the epitaxial growth of single crystal SiC films on inexpensive single crystal silicon wafers. Progress in the improvement of film morphology and the elimination of antiphase disorder is examined. Potential candidate materials for high temperature semiconductor devices are compared and SiC films are evaluated.
Electronic devices capable of operation at 500°C are required for long term Venus surface missions, as well as for in situ monitoring and control of next generation aeronautical engines. High temperature sensors and electronics can also find many applications in military, and energy and automobile industries. Various silicon carbide (SiC) sensors and electronic devices have been developed for operation at 500 °C, and a compatible packaging system is needed for long term test and deployment of these high temperature devices. High temperature co-fired ceramics (HTCC) alumina with platinum (Pt) conductor was proposed for high temperature electronic packaging. A prototype Pt/HTCC alumina packaging system including chip-level package and circuit board has been briefly reported previously for long-term electrical testing of SiC integrated circuits at 500 °C, and brief testing at much higher temperatures. HTCC alumina is an excellent dielectric material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. Pt is chemically noble and can be co-fired with HTCC alumina in air ambient producing a viable electronic packaging material system for high temperature applications. This paper presents a more detailed description of this packaging system including prototype low power packages and circuit boards based on HTCC alumina and Pt metallization for 500°C and other harsh environment applications. The key technical considerations for chip-level packaging and circuit board assembly, including materials and processes for 500 °C durable wire-bonding and SiC die attach, and integration of multi-chip circuit boards, are presented. Experimental test results of this packaging approach applied to SiC integrated circuits at 500 °C and 700°C are discussed as well.
Electronic devices capable of operation at 500°C are required for long term Venus surface missions, as well as for in situ monitoring and control of next generation aeronautical engines. High temperature sensors and electronics can also find many applications in military, and energy and automobile industries. Various silicon carbide (SiC) sensors and electronic devices have been developed for operation at 500 °C, and a compatible packaging system is needed for long term test and deployment of these high temperature devices. High temperature co-fired ceramics (HTCC) alumina with platinum (Pt) conductor was proposed for high temperature electronic packaging. A prototype Pt/HTCC alumina packaging system including chip-level package and circuit board has been briefly reported previously for long-term electrical testing of SiC integrated circuits at 500 °C, and brief testing at much higher temperatures. HTCC alumina is an excellent dielectric material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. Pt is chemically noble and can be co-fired with HTCC alumina in air ambient producing a viable electronic packaging material system for high temperature applications. This paper presents a more detailed description of this packaging system including prototype low power packages and circuit boards based on HTCC alumina and Pt metallization for 500°C and other harsh environment applications. The key technical considerations for chip-level packaging and circuit board assembly, including materials and processes for 500 °C durable wire-bonding and SiC die attach, and integration of multi-chip circuit boards, are presented. Experimental test results of this packaging approach applied to SiC integrated circuits at 500 °C and 700°C are discussed as well.
A method for growing arrays of large-area device-size films of step-free (i.e., atomically flat) SiC surfaces for semiconductor electronic device applications is disclosed. This method utilizes a lateral growth process that better overcomes the effect of extended defects in the seed crystal substrate that limited the obtainable step-free area achievable by prior art processes. The step-free SiC surface is particularly suited for the heteroepitaxial growth of 3C (cubic) SiC, AlN, and GaN films used for the fabrication of both surface-sensitive devices (i.e., surface channel field effect transistors such as HEMT's and MOSFET's) as well as high-electric field devices (pn diodes and other solid-state power switching devices) that are sensitive to extended crystal defects.
The High Temperature Integrated Electronics and Sensors (HTIES) team at the NASA Lewis Research Center is developing silicon carbide (SiC) as an enabling electronic technology for many aerospace applications. The Lewis team is focusing on the chemical vapor deposition of the thin, single-crystal SiC films from which devices are fabricated. These films, which are deposited (i.e., epitaxially "grown") on commercial wafers, must consist of a single crystal with very few structural defects so that the derived devices perform satisfactorily and reliably. Working in collaboration (NASA grant) with Professor Pirouz of Case Western Reserve University, we developed a chemical-mechanical polishing (CMP) technique for removing the subsurface polishing damage prior to epitaxial growth of the single-crystal SiC films.
Emerging wide-bandgap (WBG) semiconductor devices such as silicon carbide (SiC) metal–oxide semiconductor field-effect transistors (MOSFETs) and gallium nitride high-electron-mobility transistors can handle high power in reduced semiconductor areas better than conventional Si-based devices owing to superior material properties. With increased power loss density in a WBG-based converter and reduced die size in power modules, thermal management of power devices must be optimized for high performance. Here, we present a graphite-embedded insulated metal substrate (thermally-annealed-pyrolytic-graphite-embedded insulated metal substrate—IMSwTPG) designed for WBG power modules. Theoretical thermal performance analysis of graphite-embedded metal cores is presented, with design details for IMSwTPG with embedded graphite to replace a direct-bonded copper (DBC) substrate. The proposed IMSwTPG is compared with an aluminum nitride-based DBC substrate using finite-element thermal analysis for steady-state and transient thermal performance. The solutions’ thermal performances are compared under different coolant temperature and thermal loading conditions, and the proposed substrate's electrical performance is validated with static and dynamic characterization. Using graphite-embedded substrates, junction-to-case thermal resistance of SiC MOSFETs can be reduced up to 17%, and device current density can be increased by 10%, regardless of the thermal management strategy used to cool the substrate. Reduced transient thermal impedance of up to 40% of dies owing to increased heat capacity is validated in transient thermal simulations and experiments. The half-bridge power module's electrical performance is evaluated for on -state resistance, switching performance, and switching loss at three junction temperature conditions. The proposed substrate solution has minimal impact on conduction and switching performance of SiC MOSFETs.
This paper will give a description and status of the Advanced Power Electronics Materials and Components Technology program being conducted by the NASA Glenn Research Center for future aerospace power applications. The focus of this research program is on the following: 1) New and/or significantly improved dielectric materials for the development of power capacitors with increased volumetric efficiency, energy density, and operating temperature. Materials being investigated include nanocrystalline and composite ceramic dielectrics and diamond-like carbon films; 2) New and/or significantly improved high frequency, high temperature, low loss soft magnetic materials for the development of transformers/inductors with increased power/energy density, electrical efficiency, and operating temperature. Materials being investigated include nanocrystalline and nanocomposite soft magnetic materials; 3) Packaged high temperature, high power density, high voltage, and low loss SiC diodes and switches. Development of high quality 4H- and 6H- SiC atomically smooth substrates to significantly improve device performance is a major emphasis of the SiC materials program; 4) Demonstration of high temperature (> 200 C) circuits using the components developed above.
SiC-based high temperature power devices are being developed for aerospace systems which will require high reliability. One behavior crucial to power device reliability. To date, it has necessarily been assumed to date is that the breakdown behavior of SiC pn junctions will be similar to highly reliable silicon-based pn junctions. Challenging this assumption, we report the observation of anomalous unreliable reverse breakdown behavior in moderately doped (2-3 x 10(exp 17) cm(exp -3)) small-area 4H- and 6H-SiC pn junction diodes at temperatures ranging from 298 K (25 C) to 873 K (600 C). We propose a mechanism in which carrier emission from un-ionized dopants and deep level defects leads to this unstable behavior. The fundamental instability mechanism is applicable to all wide bandgap semiconductors whose dopants are significantly un-ionized at typical device operating temperatures.
We report on the growth of monoclinic β- and orthorhombic κ-phase Ga2O3 thin films using liquid-injection metal-organic chemical vapor deposition on highly thermally conductive 4H-SiC substrates using gallium (III) acetylacetonate or tris(2,2,6,6-tetramethyl-3,5-heptanedionato) gallium (III). Both gallium precursors produced the β phase, while only the use of the latter led to growth of κ-Ga2O3. Regardless of the used precursor, best results for β-Ga2O3 were achieved at a growth temperature of 700 °C and O2 flows in the range of 600–800 SCCM. A relatively narrow growth window was found for κ-Ga2O3, and best results were achieved for growth temperatures of 600 °C and the O2 flow of 800 SCCM. While phase-pure β-Ga2O3 was prepared, κ-Ga2O3 showed various degrees of parasitic β phase inclusions. X-ray diffraction and transmission electron microscopy confirmed a highly textured structure of β- and κ-Ga2O3 layers resulting from the presence of multiple in-plane domain orientations. Thermal conductivities of 53 nm-thick β-Ga2O3 (2.13 + 0.29/−0.51 W/m K) and 45 nm-thick κ-Ga2O3 (1.23 + 0.22/−0.26 W/m K) were determined by transient thermoreflectance and implications for device applications were assessed. Presented results suggest great potential of heterointegration of Ga2O3 and SiC for improved thermal management and reliability of future Ga2O3-based high power devices.
With the development of silicon carbide (SiC) sensors and electronic devices for operation at 500°C, compatible packaging technologies are needed for long term high temperature test and deployment of these sensors and electronic devices. 96% Al2O3ceramic is an excellent electrically insulating material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. This paper presents a packaging system for low power integrated circuits including a prototype 8-I/O chip-level package and printed circuit board (PCB) based on 96% Al2O3ceramic substrates and Au thick-film metallization for 500°C applications. The details related to designs of packages and PCBs, packaging materials, and specific packaging step recipes including wire -bonding and die-attach, are presented. Some test results of this prototype packaging approach applied to SiC integrated circuits at 500°C are reviewed.
With the development of silicon carbide (SiC) sensors and electronic devices for operation at 500°C, compatible packaging technologies are needed for long term high temperature test and deployment of these sensors and electronic devices. 96% Al2O3 ceramic is an excellent electrically insulating material with acceptable dielectric constant and low dielectric loss over wide temperature and frequency ranges. This paper presents a packaging system for low power integrated circuits including a prototype 8-I/O chip-level package and printed circuit board (PCB) based on 96% Al2O3 ceramic substrates and Au thick-film metallization for 500°C applications. The details related to designs of packages and PCBs, packaging materials, and specific packaging step recipes including wire - bonding and die-attach, are presented. Some test results of this prototype packaging approach applied to SiC integrated circuits at 500oC are reviewed.
Many lattice defects have been attributed to the lattice mismatch and the difference in the thermal coefficient of expansion between SiC and silicon (Si). Stacking faults, twins and antiphase boundaries are some of the lattice defects found in these SiC films. These defects may be a partial cause of the disappointing performance reported for the prototype devices fabricated from beta-SiC films. The objective of this research is to relieve some of the thermal stress due to lattice mismatch when SiC is epitaxially grown on Si. The compliant substrate is a silicon membrane 2-4 microns thick. The CVD process includes the buffer layer which is grown at 1360 C followed by a very thin epitaxial growth of SiC. Then the temperature is raised to 1500 C for the subsequent growth of SiC. Since silicon melts at 1415 C, the SiC will be grown on molten Silicon which is absorbed by a porous graphite susceptor eliminating the SiC/Si interface. We suspect that this buffer layer will yield less stressed material to help in the epitaxial growth of SiC.
New wide bandgap semiconductor materials are being developed to meet the diverse high temperature, -power, and -frequency demands of the aerospace industry. Two of the most promising emerging materials are silicon carbide (SiC) for high-temperature and high power applications and gallium nitride (GaN) for high-frequency and optical (blue-light-emitting diodes and lasers) applications. This past year Glenn scientists implemented a NASA-patented crystal growth process for producing arrays of device-size mesas whose tops are atomically flat (i.e., step-free). It is expected that these mesas can be used for fabricating SiC and GaN devices with major improvements in performance and lifetime. The promising new SiC and GaN devices are fabricated in thin-crystal films (known as epi films) that are grown on commercial single-crystal SiC wafers. At this time, no commercial GaN wafers exist. Crystal defects, known as screw defects and micropipes, that are present in the commercial SiC wafers propagate into the epi films and degrade the performance and lifetime of subsequently fabricated devices. The new technology isolates the screw defects in a small percentage of small device-size mesas on the surface of commercial SiC wafers. This enables atomically flat surfaces to be grown on the remaining defect-free mesas. We believe that the atomically flat mesas can also be used to grow GaN epi films with a much lower defect density than in the GaN epi films currently being grown. Much improved devices are expected from these improved low-defect epi films. Surface-sensitive SiC devices such as Schottky diodes and field effect transistors should benefit from atomically flat substrates. Also, we believe that the atomically flat SiC surface will be an ideal surface on which to fabricate nanoscale sensors and devices. The process for achieving atomically flat surfaces is illustrated. The surface steps present on the "as-received" commercial SiC wafer is also illustrated. because of the small tilt angle between the crystal "basal" plane and the polished wafer surface. These steps are used in normal SiC epi film growth in a process known as stepflow growth to produce material for device fabrication. In the new process, the first step is to etch an array of mesas on the SiC wafer top surface. Then, epi film growth is carried out in the step flow fashion until all steps have grown themselves out of existence on each defect-free mesa. If the size of the mesas is sufficiently small (about 0.1 by 0.1 mm), then only a small percentage of the mesas will contain an undesired screw defect. Mesas with screw defects supply steps during the growth process, allowing a rough surface with unwanted hillocks to form on the mesa. The improvement in SiC epi surface morphology achievable with the new technology is shown. An atomic force microscope image of a typical SiC commercial epilayer surface is also shown. A similar image of an SiC atomically flat epi surface grown in a Glenn laboratory is given. With the current screw defect density of commercial wafers (about 5000 defects/cm2), the yield of atomically free 0.1 by 0.l mm mesas is expected to be about 90 percent. This is large enough for many types of electronic and optical devices. The implementation of this new technology was recently published in Applied Physics Letters. This work was initially carried out in-house under a Director's Discretionary Fund project and is currently being further developed under the Information Technology Base Program.
Silicon carbide (SiC)'s nonlinear optical properties and applications to quantum information have recently brought attention to its potential as an integrated photonics platform. However, despite its many excellent material properties, such as large thermal conductivity, wide transparency window, and strong optical nonlinearities, it is generally a difficult material for microfabrication. Here, it is shown that directly bonded silicon-on-silicon carbide can be a high-performing hybrid photonics platform that does not require the need to form SiC membranes or directly pattern in SiC. The optimized bonding method yields defect-free, uniform films with minimal oxide at the silicon–silicon–carbide interface. Ring resonators are patterned into the silicon layer with standard, complimentary metal–oxide–semiconductor (CMOS) compatible (Si) fabrication and measure room-temperature, near-infrared quality factors exceeding 10 5 . The corresponding propagation loss is 5.7 dB cm -1 . The process offers a wafer-scalable pathway to the integration of SiC photonics into CMOS devices.
This invention is a method for the controlled growth of single-crystal semiconductor device quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.
A method for the controlled growth of single-crystal semiconductor-device-quality films of SiC polytypes on vicinal (0001) SiC wafers with low tilt angles is presented. Both homoepitaxial and heteroepitaxial SiC films can be produced on the same wafer. In particular, 3C-SiC and 6H-SiC films can be produced within selected areas of the same 6H-SiC wafer.
We report the observation of anomalous reverse breakdown behavior in moderately doped (2-3 x 10(exp 17 cm(exp -3)) small-area micropipe-free 4H- and 6H-SiC pn junction diodes. When measured with a curve tracer, the diodes consistently exhibited very low reverse leakage currents and sharp repeatable breakdown knees in the range of 140-150 V. However, when subjected to single-shot reverse bias pulses (200 ns pulsewidth, 1 ns risetime), the diodes failed catastrophically at pulse voltages of less than 100 V. We propose a possible mechanism for this anomalous reduction in pulsed breakdown voltage relative to dc breakdown voltage. This instability must be removed so that SiC high-field devices can operate with the same high reliability as silicon power devices.
The primary means to develop advanced electrical components is to develop new and improved materials for magnetic components (transformers, inductors, etc.), capacitors, and semiconductor switches and diodes. This paper will give an update of the Advanced Power Electronics and Components Technology being developed by the NASA Glenn Research Center for use in future Power Management and Distribution subsystems used in space power systems for spacecraft and lunar and planetary surface power. The initial description and status of this technology program was presented two years ago at the First International Energy Conversion Engineering Conference held at Portsmouth, Virginia, August 2003. The present paper will give a brief background of the previous work reported and a summary of research performed the past several years on soft magnetic materials characterization, dielectric materials and capacitor developments, high quality silicon carbide atomically smooth substrates, and SiC static and dynamic device characterization under elevated temperature conditions. The rationale for and the benefits of developing advanced electrical materials and components for the PMAD subsystem and also for the total power system will also be briefly discussed.