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NASA NTRS1985

Evaluation of semiconductor devices for Electric and Hybrid Vehicle (EHV) ac-drive applications, volume 1

The results of evaluation of power semiconductor devices for electric hybrid vehicle ac drive applications are summarized. Three types of power devices are evaluated in the effort: high power bipolar or Darlington transistors, power MOSFETs, and asymmetric silicon control rectifiers (ASCR). The Bipolar transistors, including discrete device and Darlington devices, range from 100 A to 400 A and from 400 V to 900 V. These devices are currently used as key switching elements inverters for ac motor drive applications. Power MOSFETs, on the other hand, are much smaller in current rating. For the 400 V device, the current rating is limited to 25 A. For the main drive of an electric vehicle, device paralleling is normally needed to achieve practical power level. For other electric vehicle (EV) related applications such as battery charger circuit, however, MOSFET is advantageous to other devices because of drive circuit simplicity and high frequency capability. Asymmetrical SCR is basically a SCR device and needs commutation circuit for turn off. However, the device poses several advantages, i.e., low conduction drop and low cost.

Lee, F. C.↗

NASA NTRS1993

Fast Overcurrent Tripping Circuit

Fast overcurrent tripping circuit designed for incorporation into power metal oxide/semiconductor field-effect transistor (MOSFET) switching circuit. Serves as fast electronic circuit breaker by sensing voltage across MOSFET's during conduction and switching MOSFET's off within 1 microsecond after voltage exceeds reference value corresponding to tripping current. Acts more quickly than Hall-effect current sensor and, in comparison with shunt current-measuring circuits, smaller and consumes less power. Also ignores initial transient overcurrents during first 5 microseconds of switching cycle.

Sullender, Craig C.↗

NASA NTRS1992

CRRES microelectronic test chip orbital data. II

Data from a MOSFET matrix on two JPL (CIT Jet Propulsion Laboratory) CRRES (Combined Release and Radiation Effects Satellite) chips, each behind different amounts of shielding, are presented. Space damage factors are nearly identical to ground test values for pMOSFETs. The results from neighboring rows of MOSFETs show similar radiation degradation. The SRD (Space Radiation Dosimeter) is used to measure the total dose accumulated by the JPL chips. A parameter extraction algorithm that does not underestimate threshold voltage shifts is used. Temperature effects are removed from the MOSFET data.

Soli, G. A.↗

NASA NTRS2000

Radiation effects on DC-DC Converters

DC-DC switching converters are circuits that can be used to convert a DC voltage of one value to another by switching action. They are increasing being used in space systems. Most of the popular DC-DC switching converters utilize power MOSFETs. However power MOSFETs, when subjected to radiation, are susceptible to degradation of device characteristics or catastrophic failure. This work focuses on the effects of total ionizing dose on converter performance. Four fundamental switching converters (buck converter, buck-boost converter, cuk converter, and flyback converter) were built using Harris IRF250 power MOSFETs. These converters were designed for converting an input of 60 volts to an output of about 12 volts with a switching frequency of 100 kHz. The four converters were irradiated with a Co-60 gamma source at dose rate of 217 rad/min. The performances of the four converters were examined during the exposure to the radiation. The experimental results show that the output voltage of the converters increases as total dose increases. However, the increases of the output voltage were different for the four different converters, with the buck converter and cuk converter the highest and the flyback converter the lowest. We observed significant increases in output voltage for cuk converter at a total dose of 24 krad (si).

Zhang, Dexin↗

NASA NTRS2002

Modeling of Gate Bias Modulation in Carbon Nanotube Field-Effect-Transistors

The threshold voltages of a carbon nanotube (CNT) field-effect transistor (FET) are derived and compared with those of the metal oxide-semiconductor (MOS) FETs. The CNT channel is so thin that there is no voltage drop perpendicular to the gate electrode plane, which is the CNT diameter direction, and this makes the CNTFET characteristics quite different from those in MOSFETs. The relation between the voltage and the electrochemical potentials, and the mass action law for electrons and holes are examined in the context of CNTs, and it is shown that the familiar relations are still valid because of the macroscopic number of states available in the CNTs. This is in sharp contrast to the cases of quantum dots. Using these relations, we derive an inversion threshold voltage V(sub Ti) and an accumulation threshold voltage V(sub Ta) as a function of the Fermi level E(sub F) in the channel, where E(sub F) is a measure of channel doping. V(sub Ti) of the CNTFETs has a much stronger dependence than that of MOSFETs, while V(sub Ta)s of both CNTFETs and MOSFETs depend quite weakly on E(sub F) with the same functional form. This means the transition from normally-off mode to normally-on mode is much sharper in CNTFETs as the doping increases, and this property has to be taken into account in circuit design.

Yamada, Toshishige↗

NASA NTRS2009

SOI CMOS Imager with Suppression of Cross-Talk

A monolithic silicon-on-insulator (SOI) complementary metal oxide/semiconductor (CMOS) image-detecting integrated circuit of the active-pixel-sensor type, now undergoing development, is designed to operate at visible and near-infrared wavelengths and to offer a combination of high quantum efficiency and low diffusion and capacitive cross-talk among pixels. The imager is designed to be especially suitable for astronomical and astrophysical applications. The imager design could also readily be adapted to general scientific, biological, medical, and spectroscopic applications. One of the conditions needed to ensure both high quantum efficiency and low diffusion cross-talk is a relatively high reverse bias potential (between about 20 and about 50 V) on the photodiode in each pixel. Heretofore, a major obstacle to realization of this condition in a monolithic integrated circuit has been posed by the fact that the required high reverse bias on the photodiode is incompatible with metal oxide/semiconductor field-effect transistors (MOSFETs) in the CMOS pixel readout circuitry. In the imager now being developed, the SOI structure is utilized to overcome this obstacle: The handle wafer is retained and the photodiode is formed in the handle wafer. The MOSFETs are formed on the SOI layer, which is separated from the handle wafer by a buried oxide layer. The electrical isolation provided by the buried oxide layer makes it possible to bias the MOSFETs at CMOS-compatible potentials (between 0 and 3 V), while biasing the photodiode at the required higher potential, and enables independent optimization of the sensory and readout portions of the imager.

Pain, Bedabrata↗

NASA NTRS2008

Nano-Multiplication-Region Avalanche Photodiodes and Arrays

Nano-multiplication-region avalanche photodiodes (NAPDs), and imaging arrays of NAPDs integrated with complementary metal oxide/semiconductor (CMOS) active-pixel-sensor integrated circuitry, are being developed for applications in which there are requirements for high-sensitivity (including photoncounting) detection and imaging at wavelengths from about 250 to 950 nm. With respect to sensitivity and to such other characteristics as speed, geometric array format, radiation hardness, power demand of associated circuitry, size, weight, and robustness, NAPDs and arrays thereof are expected to be superior to prior photodetectors and arrays including CMOS active-pixel sensors (APSs), charge-coupled devices (CCDs), traditional APDs, and microchannelplate/ CCD combinations. Figure 1 depicts a conceptual NAPD array, integrated with APS circuitry, fabricated on a thick silicon-on-insulator wafer (SOI). Figure 2 presents selected aspects of the structure of a typical single pixel, which would include a metal oxide/semiconductor field-effect transistor (MOSFET) integrated with the NAPD. The NAPDs would reside in silicon islands formed on the buried oxide (BOX) layer of the SOI wafer. The silicon islands would be surrounded by oxide-filled insulation trenches, which, together with the BOX layer, would constitute an oxide embedding structure. There would be two kinds of silicon islands: NAPD islands for the NAPDs and MOSFET islands for in-pixel and global CMOS circuits. Typically, the silicon islands would be made between 5 and 10 m thick, but, if necessary, the thickness could be chosen outside this range. The side walls of the silicon islands would be heavily doped with electron-acceptor impurities (p+-doped) to form anodes for the photodiodes and guard layers for the MOSFETs. A nanoscale reach-through structure at the front (top in the figures) central position of each NAPD island would contain the APD multiplication region. Typically, the reach-through structure would be about 0.1 microns in diameter and between 0.3 and 0.4 nm high. The top layer in the reach-through structure would be heavily doped with electron-donor impurities (n+-doped) to make it act as a cathode. A layer beneath the cathode, between 0.1 and 0.2 nm thick, would be p-doped to a concentration .10(exp 17)cu cm. A thin n+-doped polysilicon pad would be formed on the top of the cathode to protect the cathode against erosion during a metal-silicon alloying step that would be part of the process of fabricating the array.

Zheng, Xinyu↗

NASA NTRS2009

G(sup 4)FET Implementations of Some Logic Circuits

Some logic circuits have been built and demonstrated to work substantially as intended, all as part of a continuing effort to exploit the high degrees of design flexibility and functionality of the electronic devices known as G(sup 4)FETs and described below. These logic circuits are intended to serve as prototypes of more complex advanced programmable-logicdevice-type integrated circuits, including field-programmable gate arrays (FPGAs). In comparison with prior FPGAs, these advanced FPGAs could be much more efficient because the functionality of G(sup 4)FETs is such that fewer discrete components are needed to perform a given logic function in G(sup 4)FET circuitry than are needed perform the same logic function in conventional transistor-based circuitry. The underlying concept of using G(sup 4)FETs as building blocks of programmable logic circuitry was also described, from a different perspective, in G(sup 4)FETs as Universal and Programmable Logic Gates (NPO-41698), NASA Tech Briefs, Vol. 31, No. 7 (July 2007), page 44. A G(sup 4)FET can be characterized as an accumulation-mode silicon-on-insulator (SOI) metal oxide/semiconductor field-effect transistor (MOSFET) featuring two junction field-effect transistor (JFET) gates. The structure of a G(sup 4)FET (see Figure 1) is the same as that of a p-channel inversion-mode SOI MOSFET with two body contacts on each side of the channel. The top gate (G1), the substrate emulating a back gate (G2), and the junction gates (JG1 and JG2) can be biased independently of each other and, hence, each can be used to independently control some aspects of the conduction characteristics of the transistor. The independence of the actions of the four gates is what affords the enhanced functionality and design flexibility of G(sup 4)FETs. The present G(sup 4)FET logic circuits include an adjustable-threshold inverter, a real-time-reconfigurable logic gate, and a dynamic random-access memory (DRAM) cell (see Figure 2). The configuration of the adjustable-threshold inverter is similar to that of an ordinary complementary metal oxide semiconductor (CMOS) inverter except that an NMOSFET (a MOSFET having an n-doped channel and a p-doped Si substrate) is replaced by an n-channel G(sup 4)FET

Mojarradi, Mohammad↗

NASA NTRS2007

Circuit and Method for Communication Over DC Power Line

A circuit and method for transmitting and receiving on-off-keyed (OOK) signals with fractional signal-to-noise ratios uses available high-temperature silicon- on-insulator (SOI) components to move computational, sensing, and actuation abilities closer to high-temperature or high-ionizing radiation environments such as vehicle engine compartments, deep-hole drilling environments, industrial control and monitoring of processes like smelting, and operations near nuclear reactors and in space. This device allows for the networking of multiple, like nodes to each other and to a central processor. It can do this with nothing more than the already in-situ power wiring of the system. The device s microprocessor allows it to make intelligent decisions within the vehicle operational loop and to effect control outputs to its associated actuators. The figure illustrates how each node converts digital serial data to OOK 18-kHz in transmit mode and vice-versa in receive mode; though operations at lower frequencies or up to a megahertz are within reason using this method and these parts. This innovation s technique modulates a DC power bus with millivolt-level signals through a MOSFET (metal oxide semiconductor field effect transistor) and resistor by OOK. It receives and demodulates this signal from the DC power bus through capacitive coupling at high temperature and in high ionizing radiation environments. The demodulation of the OOK signal is accomplished by using an asynchronous quadrature detection technique realized by a quasi-discrete Fourier transform through use of the quadrature components (0 and 90 phases) of the carrier frequency as generated by the microcontroller and as a function of the selected crystal frequency driving its oscillator. The detected signal is rectified using an absolute-value circuit containing no diodes (diodes being non-operational at high temperatures), and only operational amplifiers. The absolute values of the two phases of the received signal are then summed and hard limited (digitized) by comparing them to a reference level and are then input into a microprocessor as a serial bit stream. The quasi-discrete Fourier transform is performed in high-temperature components (operational amplifiers, analog switches, resistors, and capacitors). The demodulated signal is a serial data stream that is input to the UART (universal asynchronous receiver transmitter) receiver pin of the microprocessor. The OOK of the carrier frequency uses the output of the UART pin as an enabling signal that drives the gate of the MOSFET. Logic low bits enable the carrier frequency (realized by using the 0 phase signal from the microcontroller, though either phase may be used) to be DC-coupled to the power supply bus through a current-limiting resistor mounted between the MOSFET drain and the supply rail. The presence of logic lows on the power supply rail is realized by carrier bursts while logic highs are realized by the absence of bursts.

Krasowski, Michael J.↗

NASA NTRS2013

Mathematical Models of the Common-Source and Common-Gate Amplifiers using a Metal-Ferroelectric-Semiconductor Field effect Transistor

Mathematical models of the common-source and common-gate amplifiers using metal-ferroelectric- semiconductor field effect transistors (MOSFETs) are developed in this paper. The models are compared against data collected with MOSFETs of varying channel lengths and widths, and circuit parameters such as biasing conditions are varied as well. Considerations are made for the capacitance formed by the ferroelectric layer present between the gate and substrate of the transistors. Comparisons between the modeled and measured data are presented in depth as well as differences and advantages as compared to the performance of each circuit using a MOSFET.

Hunt, Mitchell↗

NASA NTRS2018

Cryogenic Parametric Characterization of Gallium Nitride Switches

This report presents the parametric characterization results of four GaN field-effect transistor (FET) devices from three manufacturers, one of which is a cascode device, and compares those results to a Si power metal-oxide-semiconductor fieldeffect transistor (MOSFET) and a SiC power MOSFET. The devices were first characterized at ambient temperature, then at cryogenic temperatures down to -196 C (LN2 temperature), and finally at ambient temperature again in the event that the device parameters were permanently affected by the cryogenic temperatures. In general, the results indicate that the GaN devices show significant improvement overall at cryogenic temperatures in the parameters characterized, such as onresistance and leakage currents, compared to the Si and SiC devices. The results show that the SiC device tested should not be used at cryogenic temperatures due to the significant increase in on-resistance. The results also show that the GaN and Si parameters characterized were either not affected by the cryogenic temperatures or changed by no more than +/-20 percent post LN2 submersion. The device that exhibited the most parametric change post LN2 submersion was the SiC power MOSFET in its leakage currents.

Gonzalez, Marcelo C.↗

NASA NTRS1971

Radiation damage in MOS integrated circuits, Part 1

Complementary and p-channel MOS integrated circuits made by four commercial manufacturers were investigated for sensitivity to radiation environment. The circuits were irradiated with 1.5 MeV electrons. The results are given for electrons and for the Co-60 gamma radiation equivalent. The data are presented in terms of shifts in the threshold potentials and changes in transconductances and leakages. Gate biases of -10V, +10V and zero volts were applied to individual MOS units during irradiation. It was found that, in most of circuits of complementary MOS technologies, noticable changes due to radiation appear first as increased leakage in n-channel MOSFETs somewhat before a total integrated dose 10 to the 12th power electrons/sg cm is reached. The inability of p-channel MOSFETs to turn on sets in at about 10 to the 13th power electrons/sq cm. Of the circuits tested, an RCA A-series circuit was the most radiation resistant sample.

Danchenko, V.↗

NASA NTRS1973

P-channel silicone gate FET

Modified fabrication technique for P-channel MOSFET devices eliminates problems involving gate placement and gate overlap. Technique provides self-aligned gate, eliminating complexity of mask aligning. Devices produced by this process are considerably faster than conventional MOSFET's and process increases yield.

Ostis, S.↗

NASA NTRS1972

A linear voltage-tunable distributed null device.

A linear voltage-tunable null device was predicted, fabricated, and tested. This filter is conceptually a distributed parameter RC representation of the channel of a MOSFET in a network configuration with a second MOSFET that is treated as a variable resistor. Classical transmission-line theory is used to predict a linear tuning curve with applied bias for the device. This concept was used to design a null device having a null that is linearly tunable in the range of 100 kHz. Such devices were fabricated and tested. Typical MOS processing steps were used and the resulting structures are compatible with the planar technology. The compatibility leads towards extension of this work to different frequency ranges for other specific applications.

Benz, H. F.↗

NASA NTRS1979

A study of trends and techniques for space base electronics

The use of dry processing and alternate dielectrics for processing wafers is reported. A two dimensional modeling program was written for the simulation of short channel MOSFETs with nonuniform substrate doping. A key simplifying assumption used is that the majority carriers can be represented by a sheet charge at the silicon dioxide-silicon interface. In solving current continuity equation, the program does not converge. However, solving the two dimensional Poisson equation for the potential distribution was achieved. The status of other 2D MOSFET simulation programs are summarized.

Trotter, J. D.↗

NASA NTRS1979

Trends and Techniques for Space Base Electronics

Simulations of various phosphorus and boron diffusions in SOS were completed and a sputtering system, furnaces, and photolithography related equipment were set up. Double layer metal experiments initially utilized wet chemistry techniques. By incorporating ultrasonic etching of the vias, premetal cleaning a modified buffered HF, phosphorus doped vapox, and extended sintering, yields of 98% were obtained using the standard test pattern. A two dimensional modeling program was written for simulating short channel MOSFETs with nonuniform substrate doping. A key simplifying assumption used is that the majority carriers can be represented by a sheet charge at the silicon dioxide silicon interface. Although the program is incomplete, the two dimensional Poisson equation for the potential distribution was achieved. The status of other Z-D MOSFET simulation programs is summarized.

Trotter, J. D.↗

NASA NTRS1985

High-voltage, high-power, solid-state remote power controllers for aerospace applications

Two general types of remote power controller (RPC) that combine the functions of a circuit breaker and a switch were developed for use in direct-current (dc) aerospace systems. Power-switching devices used in these designs are the relatively new gate-turnoff thyristor (GTO) and poweer metal-oxide-semiconductor field-effect transistors (MOSFET). The various RPC's can switch dc voltages to 1200 V and currents to 100 A. Seven different units were constructed and subjected to comprehensive laboratory and thermal vacuum testing. Two of these were dual units that switch both positive and negative voltages simultaneously. The RPC's using MOSFET's have slow turnon and turnoff times to limit voltage spiking from high di/dt. The GTO's have much faster transition times. All RPC's have programmable overload tripout and microsecond tripout for large overloads. The basic circuits developed can be used to build switchgear limited only by the ratings of the switching device used.

Sturman, J. C.↗

NASA NTRS1985

Electrical performance of semiconductor devices at cryogenic temperatures

The electrical performance of semiconductor devices is examined over the temperature range from 300 to 1.4K The design, fabrication, and testing of p-channel field effective transistors (MOSFET) are emphasized to develop a device that will perform satisfactorily in the temperature range from 4.2 to 1.4K. The current-voltage characteristics of the device are obtained as a function of temperature for varying channel lengths and channel dopant levels. The MOSFET's with average channel lengths of 3.27, 5.68, 8.37, and 11.39 microns are examined. It is indicated that the devices with the shorter channel lengths perform better in the 4 to 20K range than those with the longer channel lengths.

Ventrice, C. A.↗