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At least 181 records · Page 10

Simulation of the Predictive Control Algorithm for Container Crane Operation using Matlab Fuzzy Logic Tool Box

This research has investigated the use of fuzzy logic, via the Matlab Fuzzy Logic Tool Box, to design optimized controller systems. The engineering system for which the controller was designed and simulate was the container crane. The fuzzy logic algorithm that was investigated was the 'predictive control' algorithm. The plant dynamics of the container crane is representative of many important systems including robotic arm movements. The container crane that was investigated had a trolley motor and hoist motor. Total distance to be traveled by the trolley was 15 meters. The obstruction height was 5 meters. Crane height was 17.8 meters. Trolley mass was 7500 kilograms. Load mass was 6450 kilograms. Maximum trolley and rope velocities were 1.25 meters per sec. and 0.3 meters per sec., respectively. The fuzzy logic approach allowed the inclusion, in the controller model, of performance indices that are more effectively defined in linguistic terms. These include 'safety' and 'cargo swaying'. Two fuzzy inference systems were implemented using the Matlab simulation package, namely the Mamdani system (which relates fuzzy input variables to fuzzy output variables), and the Sugeno system (which relates fuzzy input variables to crisp output variable). It is found that the Sugeno FIS is better suited to including aspects of those plant dynamics whose mathematical relationships can be determined.

Richardson, Albert O.↗

Using Pipelined XNOR Logic to Reduce SEU Risks in State Machines

Single-event upsets (SEUs) pose great threats to avionic systems state machine control logic, which are frequently used to control sequence of events and to qualify protocols. The risks of SEUs manifest in two ways: (a) the state machine s state information is changed, causing the state machine to unexpectedly transition to another state; (b) due to the asynchronous nature of SEU, the state machine's state registers become metastable, consequently causing any combinational logic associated with the metastable registers to malfunction temporarily. Effect (a) can be mitigated with methods such as triplemodular redundancy (TMR). However, effect (b) cannot be eliminated and can degrade the effectiveness of any mitigation method of effect (a). Although there is no way to completely eliminate the risk of SEU-induced errors, the risk can be made very small by use of a combination of very fast state-machine logic and error-detection logic. Therefore, one goal of two main elements of the present method is to design the fastest state-machine logic circuitry by basing it on the fastest generic state-machine design, which is that of a one-hot state machine. The other of the two main design elements is to design fast error-detection logic circuitry and to optimize it for implementation in a field-programmable gate array (FPGA) architecture: In the resulting design, the one-hot state machine is fitted with a multiple-input XNOR gate for detection of illegal states. The XNOR gate is implemented with lookup tables and with pipelines for high speed. In this method, the task of designing all the logic must be performed manually because no currently available logic synthesis software tool can produce optimal solutions of design problems of this type. However, some assistance is provided by a script, written for this purpose in the Python language (an object-oriented interpretive computer language) to automatically generate hardware description language (HDL) code from state-transition rules.

Le, Martin↗

Optimal redesign study of the harm wing

The purpose of this project was to investigate the use of optimization techniques to improve the flutter margins of the HARM AGM-88A wing. The missile has four cruciform wings, located near mid-fuselage, that are actuated in pairs symmetrically and antisymmetrically to provide pitch, yaw, and roll control. The wings have a solid stainless steel forward section and a stainless steel crushed-honeycomb aft section. The wing restraint stiffness is dependent upon wing pitch amplitude and varies from a low value near neutral pitch attitude to a much higher value at off-neutral pitch attitudes, where aerodynamic loads lock out any free play in the control system. The most critical condition for flutter is the low-stiffness condition in which the wings are moved symmetrically. Although a tendency toward limit-cycle flutter is controlled in the current design by controller logic, wing redesign to improve this situation is attractive because it can be accomplished as a retrofit. In view of the exploratory nature of the study, it was decided to apply the optimization to a wing-only model, validated by comparison with results obtained by Texas Instruments (TI). Any wing designs that looked promising were to be evaluated at TI with more complicated models, including body modes. The optimization work was performed by McIntosh Structural Dynamics, Inc. (MSD) under a contract from TI.

Mcintosh, S. C., Jr.↗

Control logic to track the outputs of a command generator or randomly forced target

A procedure is presented for synthesizing time-invariant control logic to cause the outputs of a linear plant to track the outputs of an unforced (or randomly forced) linear dynamic system. The control logic uses feed-forward of the reference system state variables and feedback of the plant state variables. The feed-forward gains are obtained from the solution of a linear algebraic matrix equation of the Liapunov type. The feedback gains are the usual regulator gains, determined to stabilize (or augment the stability of) the plant, possibly including integral control. The method is applied here to the design of control logic for a second-order servomechanism to follow a linearly increasing (ramp) signal, an unstable third-order system with two controls to track two separate ramp signals, and a sixth-order system with two controls to track a constant signal and an exponentially decreasing signal (aircraft landing-flare or glide-slope-capture with constant velocity).

Trankle, T. L.↗

Microwave brightness temperature of a windblown sea

A mathematical model is developed for the apparent temperature of the sea at all microwave frequencies. The model is a numerical model in which both the clear water structure and white water are accounted for as a function of wind speed. The model produces results similar to Stogryn's model at 19.35 GHz for wind speeds less than 8 m/sec; it can use radiosonde data to calculate atmospheric effects and can incorporate an empirically determined antenna gain pattern. The corresponding computer program is of modular design and the logic of the main program is capable of treating a horizontally inhomogeneous surface or atmosphere. It is shown that a variation of microwave brightness temperature with zenith angle is necessary to produce the wind sensitivity of the horizontally polarized brightness temperature; the variation of sky temperature with frequency is sufficient to produce a frequency dependent wind sensitivity.

Hall, F. G.↗

Aerospace vehicle synthesis program

A modified version of the Aerospace Vehicle Synthesis Program (VSP) to simulate a space shuttle on the computer is presented. The effects of various changes such as payload weight, and orbital velocity can be determined along with minimum costs in vehicle design. The program logic, and weight estimating equations are discussed, and an example case of a solid propellant boosted, drop tank orbiter is included to indicate the type of results produced by the VSP.

Source record↗

Design of a modular digital computer system, CDRL no. D001, final design plan

The engineering breadboard implementation for the CDRL no. D001 modular digital computer system developed during design of the logic system was documented. This effort followed the architecture study completed and documented previously, and was intended to verify the concepts of a fault tolerant, automatically reconfigurable, modular version of the computer system conceived during the architecture study. The system has a microprogrammed 32 bit word length, general register architecture and an instruction set consisting of a subset of the IBM System 360 instruction set plus additional fault tolerance firmware. The following areas were covered: breadboard packaging, central control element, central processing element, memory, input/output processor, and maintenance/status panel and electronics.

Easton, R. A.↗

Landsat 2 on-board computer

The Landsat Spacecraft Project (formerly known as ERTS) was based essentially on the use of Nimbus spacecraft hardware. It was soon recognized that the availability of only 30 stored command locations (which were sufficient for the Nimbus mission) would limit the operation of the Landsat 1 mission with much higher power sensors, recorders, and wideband communications being cycled on and off throughout the orbit. The solution described is a simple memory with hard wired logic, of a design that can interface with the existing hardware, without modifications. The design was implemented using an existing APO (Advanced Onboard Processor) and a 4096 word X 18 bit plated wire memory. (The AOP has been subsequently designated the NASA Standard Spacecraft Computer.)

Lesko, J. G., Jr.↗

Development of CMOS integrated circuits

Report documents life cycles of two custom CMOS integrated circuits: (1) 4-bit multiplexed register with shift left and shift right capabilities, and (2) dual 4-bit registers. Cycles described include conception as logic diagrams through design, fabrication, testing, and delivery.

Bertino, F.↗

The Massively Parallel Processor and its applications

A long-term experimental development program conducted at Goddard Space Flight Center to implement an ultrahigh-speed data processing system known as the Massively Parallel Processor (MPP) is described. The MPP is a single instruction multiple data stream computer designed to perform logical, integer, and floating point arithmetic operations on variable word length data. Information is presented on system architecture, the system configuration, the array unit architecture, individual processing units, and expected operating rates for several image processing applications (including the processing of Landsat data).

Strong, J. P.↗

Challenges in the development of the orbiter active thermal control subsystem

A number of major challenges were faced in the design and development of the Orbiter Active Thermal Control Subsystem (ATCS). At the system level, the initial challenges were to define an approach that would interface dual Freon coolant loops with multiple coolant loops from other vehicle subsystems with the lowest weight penalty to the Orbiter; and to provide highly responsive vehicle heat rejection throughout all of the Orbiter mission phases. Optimized heat exchangers, representing an advance in the state-of-the-art in heat exchanger design, were developed to transfer heat between the orbiter Freon coolant loops and five other vehicle systems. Flash evaporation was selected as a highly efficient and responsive means for cooling the Orbiter Freon loops during ascent and entry. The Flash Evaporator Subsystem (FES) utilizes cyclic water spray cooling in a chamber maintained at or below the water triple point pressure. A summary of the basic heat transfer research conducted to identify the fundamental heat transfer processes involved in water spray cooling in support of the FES design is given. The high fidelity dynamic analytical model of the FES that was generated to aid in the design of control logic, evaluate performance and simulate ground test and flight anomalies is discussed. A description of the FES and Integrated ATCS testing conducted in the SESL chamber A at NASA-JSC is also presented.

Nason, J. R.↗

Fault detection and accommodation testing on an F100 engine in an F-15 airplane

The fault detection and accommodation (FDA) methodology for digital engine-control systems may range from simple comparisons of redundant parameters to the more complex and sophisticated observer models of the entire engine system. Evaluations of the various FDA schemes are done using analytical methods, simulation, and limited-altitude-facility testing. Flight testing of the FDA logic has been minimal because of the difficulty of inducing realistic faults in flight. A flight program was conducted to evaluate the fault detection and accommodation capability of a digital electronic engine control in an F-15 aircraft. The objective of the flight program was to induce selected faults and evaluate the resulting actions of the digital engine controller. Comparisons were made between the flight results and predictions. Several anomalies were found in flight and during the ground test. Simulation results showed that the inducement of dual pressure failures was not feasible since the FDA logic was not designed to accommodate these types of failures.

Myers, L. P.↗

Fault detection and accommodation testing on an F100 engine in an F-15 airplane

The fault detection and accommodation (FDA) methods that can be used for digital engine control systems are presently subjected to a flight test program in the case of the F-15 fighter's F100 engine electronic controls, inducing selected faults and then evaluating the resulting digital engine control responses. In general, flight test results were found to compare well with both ground tests and predictions. It is noted that the inducement of dual-pressure failures was not feasible, since FDA logic was not designed to accommodate them.

Myers, L. P.↗

An expert system for air traffic control system

The objective was to design a control logic which automates all or part of the guidance function for air traffic control systems. Particular interest was focused on automation of the terminal area control system. A preliminary study was done on the development of an expert system. The system may be used to assist controllers by providing them with feasible options in guiding each aircraft in the control area to its desired destination.

Sensui, Takashi↗

VLSI high speed packet processor

The Goddard Space Flight Center Mission Operations and Data Systems Directorate has developed a packet processor card utilizing semicustom very large scale integration (VLSI) devices, microprocessors, and programmable gate arrays to support the implementation of multichannel telemetry data capture systems. This card will receive synchronized error corrected telemetry transfer frames and output annotated application packets derived from this data. An adaptable format capability is provided by the programmability of three microprocessors while the throughput capability of the packet processor is achieved by a data pipeline consisting of two separate RAM systems controlled by specially designed semicustom VLSI logic.

Grebowsky, Gerald J.↗