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Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

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At least 181 records · Page 10
All sourcesNASA NTRSDOE OSTI
DOE OSTI2017

Software and Hardware Systems in the Safety Control Systems of Nuclear Power Plants

Fundamentally new software and hardware systems for lower level automation in the safety monitoring and control systems of nuclear power plants are examined. More than a hundred software-hardware systems employing software and hardware from different manufacturers have been developed and introduced in this area. Design and functional solutions based on specific software-hardware systems are presented and comparative data on the apparatus and the use of the diversity principle are discussed.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗
DOE OSTI2021

Microstructural Analysis of Cadmium Whiskers on Long-Term-Used Hardware

A survey of cadmium plated field return hardware showed ubiquitous cadmium whisker growth. The most worn and debris-covered hardware showed the densest whisker growth. Whiskers were often found growing in agglomerates of nodules and whiskers. The hardware was rinsed with alcohol to transfer whiskers and debris from the hardware to a flat stub. Fifty whiskers were studied individually by scanning electron microscopy (SEM), including energy dispersive spectroscopy (EDS) and electron backscatter diffraction (EBSD). Most of the whiskers were single crystal, though three were found to contain grain boundaries at kinks. The whiskers ranged from 5 to 600 μm in length and 80 pct showed a $<\bar{1} 2 \bar{1} 0>$ type growth direction. This growth direction facilitates the development of low energy side faces of the whisker, (0001) and {1010}.

36 MATERIALS SCIENCE↗
DOE OSTI2023

Advances in benchmarking and round robin testing for PEM water electrolysis: Reference protocol and hardware

While the number of publications in the PEM water electrolysis community increases each year, no common ground concerning reference hardware (test cells and test bench) and testing protocols has been yet established. This would, however, be necessary for the comparability of experimental results. First attempts for such reference hardware and procedures have been made in the framework of the Task 30 Electrolysis within the Technology Collaboration Programme on Advanced Fuel Cells (AFC TCP) of the International Energy Agency (IEA). Since then, improvements of both the test hardware (test cell and components) as well as the measurement protocol were identified, and a revised methodology and key results based on a comprehensive measurement series have been obtained. A detailed protocol for testing commercial reference components with a reference laboratory test cell developed in-house by Fraunhofer ISE is presented. For evaluation of the protocol and the hardware, it was tested at three different institutions at the same time. Impedance spectroscopic and polarization data was acquired and analyzed. The obtained differences in performance were calculated to give the community an expectation window to compare own data to. Finally, the importance of a thorough temperature control and the conditioning phase are demonstrated.

08 HYDROGEN↗
DOE OSTI2022

Scaling quantum approximate optimization on near-term hardware

The quantum approximate optimization algorithm (QAOA) is an approach for near-term quantum computers to potentially demonstrate computational advantage in solving combinatorial optimization problems. However, the viability of the QAOA depends on how its performance and resource requirements scale with problem size and complexity for realistic hardware implementations. Here, we quantify scaling of the expected resource requirements by synthesizing optimized circuits for hardware architectures with varying levels of connectivity. Assuming noisy gate operations, we estimate the number of measurements needed to sample the output of the idealized QAOA circuit with high probability. We show the number of measurements, and hence total time to solution, grows exponentially in problem size and problem graph degree as well as depth of the QAOA ansatz, gate infidelities, and inverse hardware graph degree. These problems may be alleviated by increasing hardware connectivity or by recently proposed modifications to the QAOA that achieve higher performance with fewer circuit layers.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2024

Open hardware solutions in quantum technology

Quantum technologies, such as communication, computing, and sensing, offer vast opportunities for advanced research and development. While an open-source ethos currently exists within some quantum technologies, especially in quantum computer programming, we argue that there are additional advantages in developing open quantum hardware (OQH). Open quantum hardware encompasses open-source software for the control of quantum devices in labs, blueprints, and open-source toolkits for chip design and other hardware components, as well as openly accessible testbeds and facilities that allow cloud-access to a wider scientific community. We provide an overview of current projects in the OQH ecosystem, identify gaps, and make recommendations on how to close them at present. More open quantum hardware would accelerate technology transfer to and growth of the quantum industry and increase accessibility in science.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗
DOE OSTI2026

Balance of Plant Modeling and Real-Time Hardware-in-the-Loop Integration with the Microreactor Automated Control System

The advent of novel microreactor technology has driven a focused effort to explore safety and efficiency improvements that can be achieved through the use of automated system control. Development of control strategies, especially for initial demonstration, requires an adequate surrogate environment to safely research failure modes and control integration with realistic hardware delay. However, efficiency gains from control strategies are improved when the scope of controller action is expanded to include system-level dynamics such as downstream heat extraction and mass flow. For this reason, a balance-of-plant (BOP) model of a representative microreactor system has been developed using the TRANsient Simulation Framework of Reconfigurable Models library in Modelica. This model captures a reactor and primary NaK coolant loop that represent corresponding system components of the Microreactor Applications Research Validation and EvaLuation (MARVEL) design as well as a secondary coolant loop and heat extraction representative of the Microreactor Agile Non-Nuclear Experimental Test Bed (MAGNET). This model configuration allows for hardware-in-the-loop (HIL) integration with microreactor automated control system (MACS) hardware in real time through a Python-based gRPC client. Real-time simulation of model performance with emulated hardware and communication delay suggests that under independent proportional-integral-derivative control of BOP model drum dynamics and downstream heat extraction, stable power load following is achievable. A slight delay in load following, filtering of high-frequency dynamics, and localized temperature fluctation suggest room for improvement through the development of higher-level control strategies. The simulated coupling of the MAGNET facility lays the groundwork for future digital twin analysis with a coupled MACS-MAGNET HIL demonstration.

McConnell, Jono [ORNL] (ORCID:0000000238984741)↗
DOE OSTI2024

HPC Network Simulation Tuning via Automatic Extraction of Hardware Parameters

Popular HPC network interconnection simulators such as SST/macro provide a variety of configurable parameters to explore the design space of hardware components such as network interface cards (NIC), switches, and links among them. While such knobs provide flexibility to explore design trade-offs for novel hardware, manually configuring simulations for matching configurations of the existing hardware to focus on topology exploration can be cumbersome and error-prone, leading to widely inaccurate simulations. This challenge is compounded when specifications of various (proprietary) technologies are not readily available or intentionally omitted. In this work, we propose a framework to autotune the multiple network models’ simulation configurations within SST/macro using Tree-structured Parzen Estimator-based Bayesian optimization to observe the effect on simulation accuracy across different message regimes. These regimes consist of small to large message sizes and latency to bandwidth-bound messages. We provide a detailed analysis of the simulation error for four representative HPC systems. Our Bayesian optimization based autotuning framework for network models achieves a maximum of 5x improvement in accuracy over best-effort manual configurations based on available hardware specifications.

Simulation, autotuning↗
DOE OSTI2016

Verifying quantitative reliability for programs that execute on unreliable hardware

Emerging high-performance architectures are expected to contain unreliable components that may exhibit soft errors, which silently corrupt the results of computations. Full detection and masking of soft errors is challenging, expensive, and, for some applications, unnecessary. For example, approximate computing applications (such as multimedia processing, machine learning, and big data analytics) can often naturally tolerate soft errors. We introduce Rely, a programming language that enables developers to reason about the quantitative reliability of an application—namely, the probability that it produces the correct result when executed on unreliable hardware. Rely allows developers to specify the reliability requirements for each value that a function produces. We perform a static quantitative reliability analysis that verifies quantitative requirements on the reliability of an application, enabling a developer to perform sound and verified reliability engineering. The analysis takes a Rely program with a reliability specification and a hardware specification that characterizes the reliability of the underlying hardware components and verifies that the program satisfies its reliability specification when executed on the underlying unreliable hardware platform. We demonstrate the application of quantitative reliability analysis on six computations implemented in Rely.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2023

XploreNAS : Explore Adversarially Robust and Hardware-efficient Neural Architectures for Non-ideal Xbars

Compute In-Memory platforms such as memristive crossbars are gaining focus as they facilitate acceleration of Deep Neural Networks (DNNs) with high area and compute efficiencies. However, the intrinsic non-idealities associated with the analog nature of computing in crossbars limits the performance of the deployed DNNs. Furthermore, DNNs are shown to be vulnerable to adversarial attacks leading to severe security threats in their large-scale deployment. Thus, finding adversarially robust DNN architectures for non-ideal crossbars is critical to the safe and secure deployment of DNNs on the edge. This work proposes a two-phase algorithm-hardware co-optimization approach called XploreNAS that searches for hardware efficient and adversarially robust neural architectures for non-ideal crossbar platforms. We use the one-shot Neural Architecture Search approach to train a large Supernet with crossbar-awareness and sample adversarially robust Subnets therefrom, maintaining competitive hardware efficiency. Our experiments on crossbars with benchmark datasets (SVHN, CIFAR10, CIFAR100) show up to ~8–16% improvement in the adversarial robustness of the searched Subnets against a baseline ResNet-18 model subjected to crossbar-aware adversarial training. We benchmark our robust Subnets for Energy-Delay-Area-Products (EDAPs) using the Neurosim tool and find that with additional hardware efficiency–driven optimizations, the Subnets attain ~1.5–1.6× lower EDAPs than ResNet-18 baseline.

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2014

Constructing Hardware in a Scale Embedded Language

Chisel is a new open-source hardware construction language developed at UC Berkeley that supports advanced hardware design using highly parameterized generators and layered domain-specific hardware languages. Chisel is embedded in the Scala programming language, which raises the level of hardware design abstraction by providing concepts including object orientation, functional programming, parameterized types, and type inference. From the same source, Chisel can generate a high-speed C++-based cycle-accurate software simulator, or low-level Verilog designed to pass on to standard ASIC or FPGA tools for synthesis and place and route.

Bachan, John↗
DOE OSTI2019

ZFP Hardware Implementation

ZFP is a floating-point compression format gaining traction in high-performance computing applications. A software implementation has demonstrated the ability to reduce data movement across communication channels and to reduce the footprint of floating-point arrays in memory. Nevertheless, any benefit in performance is limited to the spare compute cycles available before reaching bandwidth limitations. A hardware implementation of ZFP has the potential to substantially improve HPC application performance. Hardware compression speedup over software alone on a single CPU core ranges from 15x for 1-D arrays to over 200x for 3-D arrays. The implementation of ZFP is sourced in SystemC to facilitate its evaluation in various architectures. The encode pipeline consists of several modules. Uncompressed blocks of floating-point numbers in IEEE format flow into the pipeline in a stream and a compressed bitstream flows out from the pipeline. The decode pipeline is the inverse of the encode pipeline. A modular design enables formats other than IEEE (such as posits) to be considered with minor adaptations. Best performance will be realized from the hardware ZFP unit when batches of blocks are processed at a time. The implementation supports 1-D, 2- D and 3-D blocks of floating-point numbers. The hardware implementation of ZFP has been validated with the software implementation of ZFP. C++ template parameters are used to specify the bit width of floating-point numbers and the array dimension of the encoder. A test bench program has been created with several test cases, some with continuous data that is ideal for ZFP, and others with extreme cases containing numbers near or at the maximum or minimum values supported by the number format.

Lloyd, GS↗
DOE OSTI2026

Data-driven analysis to understand GPU hardware resource usage of optimizations

With heterogeneous systems, the number of GPUs per chip increases to provide computational capabilities for solving science at a nanoscopic scale. However, low utilization for single GPUs defies the need to invest more money in expensive accelerators. Although related work develops optimizations to improve application performance, none studies how these optimizations impact hardware resource usage or average GPU utilization. Here, this paper takes a data-driven analysis approach in addressing this gap by (1) characterizing how hardware resource usage affects device utilization, execution time, or both, (2) presenting a multiobjective metric to identify important application-device interactions that can be optimized to improve device utilization and application performance jointly, (3) studying hardware resource usage behaviors of several optimizations for a benchmark application, and finally (4) identifying optimization opportunities for several scientific proxy applications based on their hardware resource usage behaviors. Furthermore, we demonstrate the applicability of our methodology by applying the identified optimizations to a proxy application, which improves the execution time, device utilization, and power consumption by up to 29.6%, 5.3% and 26.5% respectively.

Computer science↗
DOE OSTI2026

Lifetime extension of legacy CEBAF LLRF hardware

A significant portion of the Low-Level Radio Frequency (LLRF) hardware in Jefferson Lab’s CEBAF is from the original construction of the facility using 1980’s CAMAC technology. Of the fifty-three zones in CEBAF, thirty-six of them are legacy hardware. The age of the legacy system has led to difficulties in maintaining the hardware due to parts going obsolete without suitable drop in replacements. Continued operation of the legacy system is required as the installation of LLRF 3.0 systems is costly and cannot be completed in a short period of time with the available resources. The most pressing failure in the legacy system was a failing buffer card, which is responsible for communication between the EPICs network and individual RF control modules. A new buffer card was designed as a transparent, drop in, replacement so that upgrades are simply a matter of swapping the existing legacy hardware. This buffer card upgrades a single point failure component and promises to extend the operable lifetime of CEBAF’s legacy systems.

Accelerator Physics↗
DOE OSTI2015

Numerical Analysis of Fixed Point Algorithms in the Presence of Hardware Faults

The exponential growth of computational power of the extreme scale machines over the past few decades has led to a corresponding decrease in reliability and a sharp increase of the frequency of hardware faults. Our research focuses on the mathematical challenges presented by the silent hardware faults. i.e., faults that can perturb the result of computations in an inconspicuous way. Using the approach of selective reliability we present an analytic fault mode that can be used to study the resilience properties of a numerical algorithm. We apply our approach to the classical fixed point iteration and demonstrate that in the presence of hardware faults, the classical method fails to converge in expectation. We preset a modified resilient algorithm that detects and rejects faults resulting in error with large magnitude, while small faults are negated by the natural self-correcting properties of the algorithm. We show that our method is convergent (in first and second statistical moments) even in the presence of silent hardware faults.

algorithmic resilience↗
DOE OSTI2018

Hardware and Software Guidelines for the STAX Project

This document will list and describe hardware and software guidelines for the Source Term Analysis of Xenon (STAX) project. This document is intended to be technically at a high-level and therefore is not intended to define every detail related to particular hardware and software designs. Hardware and software providers will use this document as guidance for their specific designs, and any equipment provided to the STAX project should be based on these guidelines. This document was developed from technical conversations that took place at the STAX kickoff workshop. The attendees of this workshop are an international group of experts, including hardware and software providers as well as data users from NDC’s and the International Data Centre (IDC).

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2023

Modernizing Fermilab s Control Hardware

Modernizing the Fermilab accelerator control system is essential to future operations of the laboratory's accelerator complex. The existing control system has evolved over four decades and uses hardware that is no longer available. The Accelerator Controls Operations Research Network (ACORN) Project will modernize the control system and replace end-of-life power supplies to enable future accelerator complex operations with megawatt particle beams. The ACORN project is planning to replace Fermilab’s obsolete CAMAC crate-and-card controls hardware with modern MicroTCA hardware. There are over 2,000 CAMAC cards and over 250 CAMAC crates serving various functions in Fermilab’s control system. We will present an overview of the existing CAMAC hardware and the proposed MicroTCA replacement plan.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2024

Using Likwid and Byfl to Benchmark Hardware Performance

This paper outlines a benchmarking study conducted during my internship at LANL, focusing on CPU (Computer Processing Unit) and program performance assessment. The primary goal was to gather memory access data using three methods across five polybench kernels The data gathered would then be used to compare and contrast to one another and calculate operational intensity for performance comparisons. Benchmarking tools like Byfl and Likwid were employed, with Byfl offering hardware-independent data through LLVM compiler communication and Likwid directly interacting with computer hardware. The study considered various benchmarking factors, including optimization levels, Big O notation ((n)), CPU diversity and specific kernel equations. Big O notation was utilized to simplify code complexity, with detailed breakdwons of operations and memory components for each polybench application. Specific O(n) equations enabled nuanced kernel compariosns, facilitating the identification of performance variations. CPU efficiency assessments were conducted using Likwid tests on two CPUs. The central focus on code optimization aimed at achieving higher speeds and reduced memory usage through streamlined code. Future work propsoes creating a roofline model, synthesizing benchmarking data into a comprehensive data graph to assist in optimizing code and improving hardware performance. The potential impact on the laboratory or national mission was underscored, emphasizing the importance of optimizing applications and hardware to conserve resources and accelerate program execution. The specific relevance to LANL’s operations in math-intensive fields such as Nuclear Fission, Space Exploration, and Nanotechnology highlights the necessity of efficient benchmarking for resource conservation and proram speed. Overall, this study contributes to the understanding of CPU and program performance, providing insights for future optimization efforts in a laboratory setting

97 MATHEMATICS AND COMPUTING↗
DOE OSTI2022

Application of Quantum Machine Learning to High Energy Physics Analysis at LHC Using Quantum Computer Simulators and Quantum Computer Hardware

Machine learning enjoys widespread success in High Energy Physics (HEP) analyses at LHC. However the ambitious HL-LHC program will require much more computing resources in the next two decades. Quantum computing may offer speed-up for HEP physics analyses at HL-LHC, and can be a new computational paradigm for big data analyses in High Energy Physics.We have successfully employed three methods (1) Variational Quantum Classifier (VQC) method, (2) Quantum Support Vector Machine Kernel (QSVM-kernel) method and (3) Quantum Neural Network (QNN) method for two LHC flagship analyses: ttH (Higgs production in association with two top quarks) and H->mumu (Higgs decay to two muons, the second generation fermions). We shall address the progressive improvements in performance from method (1) to method (3).We will present our experiences and results of a study on LHC High Energy Physics data analyses with IBM Quantum Simulator and Quantum Hardware (using IBM Qiskit framework), Google Quantum Simulator (using Google Cirq framework), and Amazon Quantum Simulator (using Amazon Braket cloud service). The work is in the context of a Qubit platform (a gate-model quantum computer). Taking into account the present limitation of hardware access, different quantum machine learning methods are studied on simulators and the results are compared with classical machine learning methods (BDT, classical Support Vector Machine and classical Neural Network). Furthermore, we do apply quantum machine learning on IBM quantum hardware to compare performance between quantum simulator and quantum hardware. The work is performed by an international and interdisciplinary collaboration with the Department of Physics and Department of Computer Sciences of University of Wisconsin, CERN Quantum Technology Initiative, IBM Research Zurich, IBM T.J. Watson Research Center, Fermilab Quantum Institute, BNL Computational Science Initiative, State University of New York at Stony Brook, and Quantum Computing and AI Research of Amazon Web Services. This work pioneers a close collaboration of academic institutions with industrial corporations in the High Energy Physics analyses effort. Though the size of event samples in future HL-LHC physics and the limited number of qubits pose some challenges to the Quantum Machine learning studies for High Energy Physics, more advanced quantum computers with larger number of qubits, reduced noise and improved running time (as envisioned by IBM and Google) may outperform classical machine learning in both classification power and in speed.Although the era of efficient quantum computing may still be years away, we have made promising progress and obtained preliminary results in applying quantum machine learning to High Energy Physics. A PROOF OF PRINCIPLE.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗