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At least 181 records · Page 10
All sourcesNASA NTRSDOE OSTI
DOE OSTI2026

Landau–Zener Transition Enhanced Quantum Sensing in Spin Defects of Hexagonal Boron Nitride

Negatively charged boron vacancies (V $^{–}_{B}$ ) in hexagonal boron nitride (hBN) comprise a promising quantum sensing platform, optically addressable at room temperature and transferable onto samples. However, broad hyperfine-split spin transitions of the ensemble pose challenges for quantum sensing with conventional resonant excitation due to limited spectral coverage. While V $^{–}_{B}$ in isotopically enriched hBN using 10 B and 15 N isotopes (h 10 B 15 N) exhibits sharper spectral features, significant inhomogeneous broadening persists. We show that, implemented via frequency modulation on an FPGA, a frequency-ramped microwave pulse achieves around 4-fold greater |0⟩→|−1⟩ spin-state population transfer and thus contrast than resonant microwave excitation and thus 16-fold shorter measurement time for spin relaxation-based quantum sensing. Quantum dynamics simulations reveal that an effective two-state Landau–Zener model captures the complex relationship between population inversion and pulse length with relaxations incorporated. Our approach is robust and valuable for quantum relaxometry with spin defects in hBN, especially in noisy environments.

37 INORGANIC, ORGANIC, PHYSICAL, AND ANALYTICAL CH↗
DOE OSTI2023

Low Energy LArTPC Signal Detection Using Anomaly Detection

Extracting low-energy signals from LArTPC detectors is useful, for example, for detecting supernova events or calibrating the energy scale with argon-39. However, it is difficult to efficiently extract the signals because of noise. We propose using a 1DCNN to select wire traces that have a signal. This efficiently suppresses the background while still being efficient for the signal. This is then followed by a 1D autoencoder to denoise the wire traces. At that point the signal waveform can be cleanly extracted. In order to make this processing efficient, we implement the two networks on an FPGA. In particular we use hls4ml to produce HLS from the Keras models for both the 1DCNN and the autoencoder. We deploy them on an AMD/Xilinx Alveo U55C using the Vitis software platform.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
NASA NTRS2005

Reconfigurable Advanced Receiver Design and Implementation

While the demand for real-time broadband information access has grown and continues to grow at a rapid Pace, the need for a reconfigurable receiver system has increased. To achieve the goal to communicate with multiple shuttles at a time, a filter bank in polyphase structure is introduced. This paper presents the design and implementation for high-speed, high-performance, and fixed-point polyphase filter banks. The polyphase filter structure is designed such that the use of a fixed-point system has minimum impact on the performance of the filter. The final hardware implementation is done on a Xilinx FPGA chip.

Xu, Jianjing↗
NASA NTRS2006

A High-Throughput Processor for Flight Control Research Using Small UAVs

There are numerous autopilot systems that are commercially available for small (<100 lbs) UAVs. However, they all share several key disadvantages for conducting aerodynamic research, chief amongst which is the fact that most utilize older, slower, 8- or 16-bit microcontroller technologies. This paper describes the development and testing of a flight control system (FCS) for small UAV s based on a modern, high throughput, embedded processor. In addition, this FCS platform contains user-configurable hardware resources in the form of a Field Programmable Gate Array (FPGA) that can be used to implement custom, application-specific hardware. This hardware can be used to off-load routine tasks such as sensor data collection, from the FCS processor thereby further increasing the computational throughput of the system.

Klenke, Robert H.↗
NASA NTRS2010

Real-Time On-Board Processing Validation of MSPI Ground Camera Images

The Earth Sciences Decadal Survey identifies a multiangle, multispectral, high-accuracy polarization imager as one requirement for the Aerosol-Cloud-Ecosystem (ACE) mission. JPL has been developing a Multiangle SpectroPolarimetric Imager (MSPI) as a candidate to fill this need. A key technology development needed for MSPI is on-board signal processing to calculate polarimetry data as imaged by each of the 9 cameras forming the instrument. With funding from NASA's Advanced Information Systems Technology (AIST) Program, JPL is solving the real-time data processing requirements to demonstrate, for the first time, how signal data at 95 Mbytes/sec over 16-channels for each of the 9 multiangle cameras in the spaceborne instrument can be reduced on-board to 0.45 Mbytes/sec. This will produce the intensity and polarization data needed to characterize aerosol and cloud microphysical properties. Using the Xilinx Virtex-5 FPGA including PowerPC440 processors we have implemented a least squares fitting algorithm that extracts intensity and polarimetric parameters in real-time, thereby substantially reducing the image data volume for spacecraft downlink without loss of science information.

Earth Sciences Decadal Survey↗
NASA NTRS2010

A High-Throughput, Adaptive FFT Architecture for FPGA-Based Space-Borne Data Processors

Historically, computationally-intensive data processing for space-borne instruments has heavily relied on ground-based computing resources. But with recent advances in functional densities of Field-Programmable Gate-Arrays (FPGAs), there has been an increasing desire to shift more processing on-board; therefore relaxing the downlink data bandwidth requirements. Fast Fourier Transforms (FFTs) are commonly used building blocks for data processing applications, with a growing need to increase the FFT block size. Many existing FFT architectures have mainly emphasized on low power consumption or resource usage; but as the block size of the FFT grows, the throughput is often compromised first. In addition to power and resource constraints, space-borne digital systems are also limited to a small set of space-qualified memory elements, which typically lag behind the commercially available counterparts in capacity and bandwidth. The bandwidth limitation of the external memory creates a bottleneck for a large, high-throughput FFT design with large block size. In this paper, we present the Multi-Pass Wide Kernel FFT (MPWK-FFT) architecture for a moderately large block size (32K) with considerations to power consumption and resource usage, as well as throughput. We will also show that the architecture can be easily adapted for different FFT block sizes with different throughput and power requirements. The result is completely contained within an FPGA without relying on external memories. Implementation results are summarized.

Nguyen, Kayla↗
DOE OSTI2024

Low latency optical-based mode tracking with machine learning deployed on FPGAs on a tokamak

Active feedback control in magnetic confinement fusion devices is desirable to mitigate plasma instabilities and enable robust operation. Optical high-speed cameras provide a powerful, non-invasive diagnostic and can be suitable for these applications. Here, in this study, we process high-speed camera data, at rates exceeding 100 kfps, on in situ field-programmable gate array (FPGA) hardware to track magnetohydrodynamic (MHD) mode evolution and generate control signals in real time. Our system utilizes a convolutional neural network (CNN) model, which predicts the n = 1 MHD mode amplitude and phase using camera images with better accuracy than other tested non-deep-learning-based methods. By implementing this model directly within the standard FPGA readout hardware of the high-speed camera diagnostic, our mode tracking system achieves a total trigger-to-output latency of 17.6 μs and a throughput of up to 120 kfps. This study at the High Beta Tokamak-Extended Pulse (HBT-EP) experiment demonstrates an FPGA-based high-speed camera data acquisition and processing system, enabling application in real-time machine-learning-based tokamak diagnostic and control as well as potential applications in other scientific domains.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
NASA NTRS2008

Using Pipelined XNOR Logic to Reduce SEU Risks in State Machines

Single-event upsets (SEUs) pose great threats to avionic systems state machine control logic, which are frequently used to control sequence of events and to qualify protocols. The risks of SEUs manifest in two ways: (a) the state machine s state information is changed, causing the state machine to unexpectedly transition to another state; (b) due to the asynchronous nature of SEU, the state machine's state registers become metastable, consequently causing any combinational logic associated with the metastable registers to malfunction temporarily. Effect (a) can be mitigated with methods such as triplemodular redundancy (TMR). However, effect (b) cannot be eliminated and can degrade the effectiveness of any mitigation method of effect (a). Although there is no way to completely eliminate the risk of SEU-induced errors, the risk can be made very small by use of a combination of very fast state-machine logic and error-detection logic. Therefore, one goal of two main elements of the present method is to design the fastest state-machine logic circuitry by basing it on the fastest generic state-machine design, which is that of a one-hot state machine. The other of the two main design elements is to design fast error-detection logic circuitry and to optimize it for implementation in a field-programmable gate array (FPGA) architecture: In the resulting design, the one-hot state machine is fitted with a multiple-input XNOR gate for detection of illegal states. The XNOR gate is implemented with lookup tables and with pipelines for high speed. In this method, the task of designing all the logic must be performed manually because no currently available logic synthesis software tool can produce optimal solutions of design problems of this type. However, some assistance is provided by a script, written for this purpose in the Python language (an object-oriented interpretive computer language) to automatically generate hardware description language (HDL) code from state-transition rules.

Le, Martin↗
NASA NTRS2012

RFI Risk Reduction Activities Using New Goddard Digital Radiometry Capabilities

The Goddard Radio-Frequency Explorer (GREX) is the latest fast-sampling radiometer digital back-end processor that will be used for radiometry and radio-frequency interference (RFI) surveying at Goddard Space Flight Center. The system is compact and deployable, with a mass of about 40 kilograms. It is intended to be flown on aircraft. GREX is compatible with almost any aircraft, including P-3, twin otter, C-23, C-130, G3, and G5 types. At a minimum, the system can function as a clone of the Soil Moisture Active Passive (SMAP) ground-based development unit [1], or can be a completely independent system that is interfaced to any radiometer, provided that frequency shifting to GREX's intermediate frequency is performed prior to sampling. If the radiometer RF is less than 200MHz, then the band can be sampled and acquired directly by the system. A key feature of GREX is its ability to simultaneously sample two polarization channels simultaneously at up to 400MSPS, 14-bit resolution each. The sampled signals can be recorded continuously to a 23 TB solid-state RAID storage array. Data captures can be analyzed offline using the supercomputing facilities at Goddard Space Flight Center. In addition, various Field Programmable Gate Array (FPGA) - amenable radiometer signal processing and RFI detection algorithms can be implemented directly on the GREX system because it includes a high-capacity Xilinx Virtex-5 FPGA prototyping system that is user customizable.

Bradley, Damon↗
DOE OSTI2021

Accelerating Transformer-based Deep Learning Models on FPGAs using Column Balanced Block Pruning

Although Transformer-based language representations achieve state-of-the-art accuracy on various natural language processing (NLP) tasks, the large model size has been challenging the resource constrained computing platforms. Weight pruning, as a popular and effective technique in reducing the number of weight parameters and accelerating the Transformer, has been investigated on GPUs. However, the Transformer acceleration using weight pruning on field-programmable gate array (FPGAs) remains unexplored. This paper investigates the column balanced block-wise pruning on Transformer and designs an FPGA acceleration engine to customize the balanced blockwise matrix multiplication. We implement the Transformer model with proper hardware scheduling, and the experiments show that the Transformer inference on FPGA achieves 10.35 ms latency with the batch size of 32, which is 10.96 × speed up comparing to CPU platform and 2.08 × speed up comparing to GPU platform.

Peng, Hongwu↗
NASA NTRS2004

A Discussion of Using a Reconfigurable Processor to Implement the Discrete Fourier Transform

This paper presents the design and implementation of the Discrete Fourier Transform (DFT) algorithm on a reconfigurable processor system. While highly applicable to many engineering problems, the DFT is an extremely computationally intensive algorithm. Consequently, the eventual goal of this work is to enhance the execution of a floating-point precision DFT algorithm by off loading the algorithm from the computing system. This computing system, within the context of this research, is a typical high performance desktop computer with an may of field programmable gate arrays (FPGAs). FPGAs are hardware devices that are configured by software to execute an algorithm. If it is desired to change the algorithm, the software is changed to reflect the modification, then download to the FPGA, which is then itself modified. This paper will discuss methodology for developing the DFT algorithm to be implemented on the FPGA. We will discuss the algorithm, the FPGA code effort, and the results to date.

White, Michael J.↗
DOE OSTI2023

The Tiny Triplet Finder as a Versatile Track Segment Seeding Engine for Trigger Systems

In high energy physics experiment trigger systems, track segment seeding is a resource consuming function and the primary reason is the computing complexity of the segment finding process. As the Moore's Law is reaching its physical limit, reducing computing complexity should be carefully considered, rather than keep piling up silicon resources. The Tiny Triplet Finder is a scheme that reduces the computing complexity of the segment seeding. As a proof of concept, a 3D track segment seeding engine core based on the Tiny Triplet Finder has been implemented and tested in a low-cost FPGA device. The seeding engine is designed to preselect and group hits (stubs) from detector layers to feed subsequent track fitting stage. The seeding engine consists of a Hough transform space for r-z view and a Tiny Triplet Finder for r-phi view to implement 3D constraints. The seeding engine is organized as a pipeline so that each hit is processed in a single clock cycle. Taking advantage of the register-like storage block scheme which enables effectively resetting of a block RAM within a single clock cycle, clearing or refreshing the seeding engine takes only one clock cycles between two events. The Tiny Triplet Finder is also a generic coincidence finding scheme that can be used for many tasks. As a versatility demonstration, track segment finding performances for two distinctive detector geometries are tested in our seeding engine. In a collider barrel-layer geometry, the fake segment rates are studied for 3D (i.e., both r-phi and r-z views) and 2D (i.e., r-phi or r-z view only) configurations for high hit multiplicity events (>4000 hits/layer in the barrel region). Another detector geometry contains strip plane layers with timing information. The numbers of coincidences, both real or fake, with or without timing ("3D" or "2D") information at various hit multiplicities are studied.

43 PARTICLE ACCELERATORS↗
DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.

Guerrero, Sasha Camila [North Central Coll.]↗
DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.

Guerrero, Sasha Camila [North Central Coll.]↗
NASA NTRS2014

System for Configuring Modular Telemetry Transponders

A system for configuring telemetry transponder cards uses a database of error checking protocol data structures, each containing data to implement at least one CCSDS protocol algorithm. Using a user interface, a user selects at least one telemetry specific error checking protocol from the database. A compiler configures an FPGA with the data from the data structures to implement the error checking protocol.

Varnavas, Kosta A.↗
DOE OSTI2024

Bridging the Gap Between LLMs and LNS with Dynamic Data Format and Architecture Codesign

Deep neural networks (DNNs) have achieved tremendous success in the past few years. However, their training and inference demand exceptional computational and memory resources. Quantization has been shown as an effective approach to mitigate the cost, with the mainstream data types reduced from FP32 to FP16/BF16 and recently FP8 in the latest NVIDIA H100 GPUs. With increasingly aggressive quantization, however, the conventional floating-point formats suffer from limited precision in representing numbers around zero. Recently, NVIDIA demonstrated the potential of using a Logarithmic Number System (LNS) for the next generation of tensor cores. While LNS mitigates the hurdles in representing small numbers, in this work we observed a mismatch between LNS and the emerging Large Language Models (LLM), where LLM exhibits significant outliers when directly adopting the LNS format. In this paper, we present a data-format/architecture codesign to bright this gap. On the format side, we propose a dynamic LNS format to flexibly represent outliers at a higher precision, by exploiting asymmetry in the LNS representation and identifying outliers through a per-vector basis. On the architecture side, for demonstration, we realize the dynamic LNS format in a systolic array, which can handle the irregularity of the outliers at runtime. We implement our approach on an Alveo U280 FPGA as a prototype. Experimental results show that our design can effectively handle the outliers and resolve the mismatch between LNS and LLM, contributing to an accuracy improvement of 15.4% and 16% over the floating-point and the original LNS baselines, using four state-of-the-art LLM models. Our observation and design lay a solid foundation for the large-scale adoption of the LNS format in the next-generation deep learning hardware.

Haghi, Pouya↗
DOE OSTI2023

Improving Signal-to-Noise Ratio (SNR) for Readout Signals Using Adaptive Filters on Reconfigurable Controls Hardware

This study investigates the optimization of Signal-to-Noise Ratio (SNR) in superconducting quantum computing readout signals through adaptive filtering. Quantum computing technology has the potential to revolutionize various fields by delivering exponential speedup in solving certain computational problems. However, the technology's practical implementation is hindered by the difficulty of extracting clean, reliable signals during the readout phase, with various sources of noise presenting a significant barrier to clean signals. This noise, often present in readout profiles due to imperfect isolation, degrades the system's overall SNR, thus impeding the ability to extract the quantum state accurately. The research leverages the power of adaptive filtering to improve the SNR of quantum computing readout signals. Specifically, an adaptive filter is implemented in a PYNQ overlay on an FPGA, and eventually will be connected to a quantum computing system. The system models the noise with a Least Mean Squares (LMS) adaptive filter, and then subtracts the estimated noise from the received signal to improve the SNR. A Direct Memory Access (DMA) channel is used to handle the signal processing, delivering efficient, high-speed data transfer between the PYNQ system and the hardware. The study explores the benefits of this adaptive filtering technique, potentially providing a significant contribution to practical and fast quantum computing.

Johnson, Hans↗