SEARCH · Engineering Papers

Results for “Digital circuits”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

SourceResearch connectionFrom yearThrough year

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 181 records · Page 10

All sources NASA NTRS DOE OSTI

DOE OSTI2026

Graphical User Interface for a Biasing Board for the PSEC6

The PSEC6 is an application-specific integrated circuit (ASIC) designed for a readout system for a large area picosecond photodetector (LAPPD). The PSEC6 is currently in fabrication and pending testing. The testing system for the PSEC5, the previous iteration of the ASIC, required expensive and non-portable equipment, because the ASIC needs twelve adjustable reference voltages. The new testing system consists of an low-cost, open-source, cross-platform graphical user interface (GUI), a digital system, and a biasing board. The digital system is the interface between the GUI and biasing board, and can be implemented on a microcontroller or field-programmable gate array (FPGA). The biasing board contains twelve digital-to-analog converters (DACs) that are configurable via the GUI, which gives users the ability to write voltage values to all or specific DACs. The GUI was developed in C on Linux using the widget library GTK4 and cross-compiled for Windows compatibility. I2C and SPI protocols were implemented on an Adafruit Feather ESP32-S3 microcontroller to write commands to the DACs and PSEC6. A hardware implementation of the I2C protocol is in development on an FPGA. Since LAPPDs will be used by the Accelerator Neutrino Neutron Interaction Experiment (ANNIE) at Fermilab, the PSEC6 testing system in this internship project can potentially benefit future neutrino research. The project is relevant to the Department of Energy’s microelectronics mission, because the PSEC6 is an ASIC that will handle fast time signals arriving from the detector for readout. It also provided experience with building a cross-platform user interface, practicing digital design and implementation in hardware description language (HDL), and using simulations to inform new design iterations.

Guerrero, Sasha Camila [North Central Coll.]↗

DOE OSTI2021

Traveling Wave Relays for Distribution Feeder Protection with High Penetrations of Distributed Energy Resources

Increased penetration of power electronics interfaced Distributed Energy Resources (DER) like PV, electric vehicle and battery storage in the distribution system (both in numbers and sizes) may cause bi-directional power flows under normal operation. In addition, they contribute low fault current under short circuit conditions. These two changes can impact the proper operation of legacy protection systems. This can add additional challenges during weak grid and islanded operation. In this research, traveling wave (high frequency) signature based protection scheme is proposed for future distribution systems. Simulations are performed under different transient scenarios to provide insight into the high frequency signatures to show the traveling wave behavior. Finally, this paper discusses the importance of sensing and digital processing requirements for traveling-wave protection in distribution system.

41 EE - Solar Energy Technologies Office (EE-4S)↗

DOE OSTI2021

Traveling Wave Relays for Distribution Feeder Protection with High Penetrations of Distributed Energy Resources: Preprint

41 EE - Solar Energy Technologies Office (EE-4S)↗

DOE OSTI2021

Traveling Wave Relays for Distribution Feeder Protection with High Penetrations of Distributed Energy Resources

41 EE - Solar Energy Technologies Office (EE-4S)↗

DOE OSTI2022

DRIPS: Dynamic Rebalancing of Pipelined Streaming Applications on CGRAs

Coarse-grained reconfigurable arrays (CGRAs) provide higher flexibility than application-specific integrated circuits (ASICs) and higher efficiency than fine-grained reconfigurable devices such as Field Programmable Gate Arrays (FPGAs). However, CGRAs are generally designed to support offloading of a single kernel. While their design, based on communicating functional units, appears to naturally suit data streaming applications composed of multiple cooperating kernels, current approaches only statically partition the resources across application kernels. However, emerging streaming applications at the edge (scientific instruments, sensor networks, network processing) perform much more than digital signal processing and often are data and input dependent. This leads to extremely variable kernel execution times, severely impacting the throughput of the entire pipeline if resources are only statically allocated. Therefore, in this paper, we propose DRIPS — a coarse-grained, dynamically, and partially reconfigurable array for data-dependent streaming applications. We present a unified compiler framework to facilitate the mapping of a given streaming application onto the DRIPS CGRA architecture. The experimental results show that DRIPS achieves an average throughput improvement of 1.46$\times$ across a set of representative applications over a statically partitioned solution. The additional area overhead to enable dynamic rebalancing consumes 16.34% of the entire area for a 5x5 CGRA prototype.

Tan, Cheng↗

DOE OSTI2025

Ground state energy and magnetization curve of a frustrated magnetic system from real-time evolution on a digital quantum processor

Models of interacting many-body quantum systems that may realize new exotic phases of matter, notably quantum spin liquids, are challenging to study using even state-of-the-art classical methods such as tensor network simulations. Quantum computing provides a promising route for overcoming these difficulties to find ground states, dynamics, and more. In this paper, we argue that recently developed hybrid quantum-classical algorithms based on real-time evolution are promising methods for solving a particularly important model in the search for spin liquids, the antiferromagnetic Heisenberg model on the two-dimensional kagome lattice. We show how to construct efficient quantum circuits to implement time evolution for the model and to evaluate key observables on the quantum computer, and we argue that the method has favorable scaling with increasing system size. We then restrict to a 12-spin star plaquette from the kagome lattice and a related 8-spin system, and we give an empirical demonstration on these small systems that the hybrid algorithms can efficiently find the ground state energy and the magnetization curve. For these demonstrations, we use four levels of approximation: exact state vectors, exact state vectors with statistical noise from sampling, noisy classical emulators, and (for the 8-spin system only) real quantum hardware, specifically the Quantinuum H1-1 processor; for the noisy simulations and hardware demonstration, we also employ error mitigation strategies based on the symmetries of the Hamiltonian. Our results strongly suggest that these hybrid algorithms present a promising direction for studying quantum spin liquids and more generally for resolving important unsolved problems in condensed matter theory and beyond.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2020

Driven-dissipative quantum mechanics on a lattice: Simulating a fermionic reservoir on a quantum computer

The driven-dissipative many-body problem remains one of the most challenging unsolved problems in quantum mechanics. The advent of quantum computers may provide a unique platform for efficiently simulating such driven-dissipative systems. But, there are many choices for how one can engineer the reservoir. One can simply employ ancilla qubits to act as a reservoir and then digitally simulate them via algorithmic cooling. A more attractive approach, which allows one to simulate an infinite reservoir, is to integrate out the bath degrees of freedom and describe the driven-dissipative system via a master equation, that can also be simulated on a quantum computer. In this work, we consider the particular case of noninteracting electrons on a lattice driven by an electric field and coupled to a fermionic thermostat. Then, we provide two different quantum circuits: the first one reconstructs the full dynamics of the system using Trotter steps, while the second one dissipatively prepares the final nonequilibrium steady state in a single step. We run both circuits on the IBM quantum experience. For circuit (i), we achieved up to five Trotter steps. When partial resets become available on quantum computers, we expect that the maximum simulation time can be significantly increased. Lastly, the methods developed here suggest generalizations that can be applied to simulating interacting driven-dissipative systems.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

DOE OSTI2022

Medium Voltage Energy Hub Based on Multilevel Cascaded H Bridge-Dual Active Bridge Back-to-Back Converter for Power Distribution Feeders Interconnection and Multiple Simultaneous Grid Services

This paper presents a medium voltage energy hub based on a modular design of a multilevel cascaded H bridge (CHB)-dual active bridge (DAB) converter. The energy hub composed of the two CHB-DAB modules with a back-to-back topology can be utilized as a grid interconnection component between distribution feeders. The energy hub can provide multiple simultaneous grid services such as voltage regulation, power factor correction, as well as active power flow control between the connected feeders, contributing to grid flexibility, efficiency, reliability, and resilience. Circuit structure and control schemes for the energy hub including both local controllers for each converter and outer loop controllers are proposed to enable simultaneous grid services with coordination to prevent the overloading of the hub. To validate the performance of the hub, the hub system is interconnected between two IEEE 4-bus feeders and provides voltage regulation for both feeders, while controlling active power flow between them. The system and the feeders are implemented in Real-Time Digital Simulator (RTDS) for real-time simulation verification.

Choi, Jongchan↗

DOE OSTI2025

Unification of finite symmetries in the simulation of many-body systems on quantum computers

Symmetry is fundamental in the description and simulation of quantum systems. Leveraging symmetries in classical simulations of many-body quantum systems can result in significant overhead due to the exponentially growing size of some symmetry groups as the number of particles increases. Quantum computers hold the promise of achieving exponential speedup in simulating quantum many-body systems; however, a general method for utilizing symmetries in quantum simulations has not yet been established. In this work, we present a unified framework for incorporating symmetry group transforms on quantum computers to simulate many-body systems. The core of our approach lies in the development of efficient quantum circuits for symmetry-adapted projection onto irreducible representations of a group or pairs of commuting groups. We provide resource estimations for common groups, including the cyclic and permutation groups. Our algorithms demonstrate the capability to prepare coherent superpositions of symmetry-adapted states and to perform quantum evolution across a wide range of models in condensed-matter physics and ab initio electronic structure in quantum chemistry. Specifically, we execute a symmetry-adapted quantum subroutine for small molecules in first-quantization on noisy hardware and demonstrate the emulation of symmetry-adapted quantum phase estimation for preparing coherent superpositions of quantum states in various irreducible representations of a symmetry group. In addition, we present a discussion of open problems regarding treating symmetries in digital quantum simulations of many-body systems, paving the way for future systematic investigations into leveraging symmetries quantumly for practical quantum advantage. The broad applicability and rigorous resource estimation for symmetry transformations make our framework appealing for achieving provable quantum advantage on fault-tolerant quantum computers, especially for symmetry-related properties.

quantum algorithms↗

DOE OSTI2024

Petahertz electronics

Petahertz, or lightwave, electronics uses tailored optical waveforms to control charge carriers in an electronic circuit at petahertz frequencies. This may enable faster processing than conventional pulsed electronics, which cannot be scaled beyond gigahertz frequencies. In recent years, petahertz-scale currents driven by optical fields have been measured in solid-state systems and nanoscale structures, with several proof-of-principle demonstrations of sub-optical-cycle current generation and optical-field-resolved waveform detection at the sub-femtosecond to few-femtosecond scale. Recent work has taken the first steps towards digital and quantum operation by exploring optical-field-driven logic and memory functionality. Here, in this Review, we discuss the progress towards sub-cycle field-driven current injection, highlighting key theoretical concepts, experimental milestones, and questions remaining as we push towards realizing petahertz electronics for ultrafast optical waveform analysis, digital logic, communications, and quantum computation.

Heide, Christian↗

DOE OSTI2020

Analog architectures for neural network acceleration based on non-volatile memory

Analog hardware accelerators, which perform computation within a dense memory array, have the potential to overcome the major bottlenecks faced by digital hardware for data-heavy workloads such as deep learning. Exploiting the intrinsic computational advantages of memory arrays, however, has proven to be challenging principally due to the overhead imposed by the peripheral circuitry and due to the non-ideal properties of memory devices that play the role of the synapse. We review the existing implementations of these accelerators for deep supervised learning, organizing our discussion around the different levels of the accelerator design hierarchy, with an emphasis on circuits and architecture. We explore and consolidate the various approaches that have been proposed to address the critical challenges faced by analog accelerators, for both neural network inference and training, and highlight the key design trade-offs underlying these techniques.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2022

Reconfigurable perovskite nickelate electronics for artificial intelligence

Reconfigurable devices offer the ability to program electronic circuits on demand. Here, in this work, we demonstrated on-demand creation of artificial neurons, synapses, and memory capacitors in post-fabricated perovskite NdNiO 3 devices that can be simply reconfigured for a specific purpose by single-shot electric pulses. The sensitivity of electronic properties of perovskite nickelates to the local distribution of hydrogen ions enabled these results. With experimental data from our memory capacitors, simulation results of a reservoir computing framework showed excellent performance for tasks such as digit recognition and classification of electrocardiogram heartbeat activity. Using our reconfigurable artificial neurons and synapses, simulated dynamic networks outperformed static networks for incremental learning scenarios. The ability to fashion the building blocks of brain-inspired computers on demand opens up new directions in adaptive networks.

75 CONDENSED MATTER PHYSICS, SUPERCONDUCTIVITY AND↗

DOE OSTI2022

Design and Challenges of Edge Computing ASICs on Front-End Electronics

In situ or hardware-embedded data processing of raw signals, close to their source, in radiation detectors is expected to provide dramatic improvements in data quality and volumes. However, the implementation of artificial neural networks (ANNs) in the front-end electronics, and the design of custom integrated circuits (ASICs), comes with challenges. In addition, detectors have to operate with limited power budget and implement complex functionalities in a very dense space. They often are exposed to extreme conditions as they work in high-radiation environments and/or cryogenic temperatures. This paper presents examples of applications and design methodologies for in-situ ANNs, along with the challenges of retaining the fidelity of the trained networks. For illustration, we use the problem of estimating the energy deposited by the radiation from digitized waveforms. The proposed implementation starts with an ML algorithm trained in Qkeras and eventually leads to an equivalent ASIC implementation. The associated design challenges in realizing energy and area efficient implementations in CMOS processes are reviewed. Novel approaches that employ hybrid technologies (combination of CMOS with memristors), in-memory computing models, and bio-inspired spiking neural networks are also highlighted

47 OTHER INSTRUMENTATION↗

DOE OSTI2022

Radiation-Hardened GaN-Based Wireless Communications Architectures for Terrestrial Nuclear Reactor Sensing and Instrumentation

Wireless technologies have become increasingly common in applications, ranging from close proximity inductive communication links in medical devices to short-range Bluetooth and WiFi communications and longer-range cellular communications. Nonetheless, these technologies are unsuitable for use in or around nuclear reactors due to the extreme radiation and temperatures inherent in these environments and their associated significant degradative effects on electronics hardware. However, recent work in wide bandgap– based electronics has shown promise for gallium nitride (GaN) as an emerging technology for the realization of practical wireless communications systems for use in harsh environments. This report presents initial progress on the development of wireless communications architectures designed specifically for nuclear reactor application, based on inherently radiation-hardened (rad-hard) GaN technology. Prior work on rad-hard analog communications topologies is reviewed, and several digital modulation and encoding schemes that utilize GaN-based electronics devices are newly proposed for application in reactor environments. Continuous-time and discrete-time system simulations were performed, and results are presented for the preliminary transmitter and receiver designs, respectively. In addition, an overview of a software-defined radio testbed, designed for communications protocol development, is provided. Future work will focus on implementing candidate radiation-resistant wireless architectures using a research AlGaN/GaN high electron mobility transistor (HEMT) integrated circuit process, which is available at the Ohio State University, and irradiation studies will be carried out to assess the true potential of this technology for reactor application.

22 GENERAL STUDIES OF NUCLEAR REACTORS↗

DOE OSTI2025

The ETROC2 as the Final Version for CMS Endcap Timing Layer (ETL) Upgrade

The ETROC (Endcap Timing Readout Chip) is being developed for the LGAD-based CMS Endcap Timing Layer (ETL) at HL-LHC. The ETL on each side of the interaction region will be instrumented with a two-disk system of MIP-sensitive LGAD (Low Gain Avalanche Diodes) silicon devices, read out by ETROCs for precision timing measurement with down to ~30 ps timing resolution per track. The ETROC is designed to handle a 16 x 16 pixel cell matrix, with each pixel being 1.3 mm x 1.3 mm to match the LGAD sensor pixel size. The front-end design for preamplifier and discriminator has been specifically optimized for the reduced LGAD signals, with enough flexibilities to meet the ETL specific needs for time resolution, power budget and radiation profile. The ETROC chip is implemented in a commercial 65nm CMOS process. Each channel consists of a preamplifier, a discriminator, a TDC used for TOA (Time Of Arrival) and TOT (Time Over Threshold) measurements, and a memory for data storage and readout. An in-pixel auto threshold calibration is included, along with a self-testing pattern generator. The TOT is used for time-walk correction of the TOA measurement. The detailed hit information (TOA and TOT) from each cell will be read out from a local circular buffer after each Level-1 Accept (about 1 MHz). In addition, a charge injection circuit is implemented to allow for testing and calibration. For more detailed monitoring of the signal pulses, waveform sampling circuits are included for one pixel. The clock distribution is based on a 16x16 H-tree design with a shielding structure to alleviate potential interference. The global peripheral circuits include a PLL, a phase shifter, an I2C slave controller, a fast control block, a global readout, and a data driver along with an efuse and temperature sensor. The ETROC builds event data frames for each L1A selected event and is also capable of providing L1 trigger information for user-defined delayed hits. The main design challenge is how to extract precision timing information from the small LGAD signals in the presence of high irradiation fluence, while keeping the power consumption and digital activity low. The ETL design goal for the time resolution of 50 ps per hit is required to achieve a 35 ps arrival time measurement for a MIP particle, which has its track registered in two ETL disk layers. The LGAD contribution is known to be about 30 ps, this means that the jitter from the ETROC has to be kept below 40 ps. The ETROC2 is the first full size full functionality prototype design fully compatible with the final chip specifications for CMS ETL and now becomes the final version. The ETROC2 chips have been extensively tested. We will present here new testing results including the bump bonding yield improvement study, the time walk correction (TWC) generality study with one pixel TWC applying to all pixels, the final SEU testing using both heavy ion and proton beam, more beam test studies including different sensors, and readiness for the ETROC2 production for CMS ETL upgrade.

Liu, Tiehui [Fermilab] (ORCID:0009000765225605)↗

DOE OSTI2020

Benchmarking noise extrapolation with the OpenPulse control framework

Distilling precise estimates from noisy intermediate scale quantum (NISQ) data has recently attracted considerable attention Kandala et al., Nature (London) 567, 491 (2019). In order to augment digital qubit metrics, such as gate fidelity, we discuss analog error mitigability, i.e., the ability to accurately distill precise observable estimates, as a hybrid quantum classical computing benchmarking task. Specifically, using Rabi oscillations as a test program, we characterize single qubit error rates on IBM's Poughkeepsie superconducting quantum hardware, incorporate control-mediated noise dependence into a generalized rescaling protocol, and analyze how noise characteristics influence Richardson extrapolation-based error mitigation. Finally, our results identify regions in the space of Hamiltonian control fields and circuit depth which are most amenable to reliable noise extrapolation, as well as shed light on how low-level hardware characterization can be used as a predictive tool for uncertainty quantification in error-mitigated NISQ computations.

71 CLASSICAL AND QUANTUM MECHANICS, GENERAL PHYSIC↗

DOE OSTI2024

Entropy Analysis of FPGA Interconnect and Switch Matrices for Physical Unclonable Functions

Random variations in microelectronic circuit structures represent the source of entropy for physical unclonable functions (PUFs). In this paper, we investigate delay variations that occur through the routing network and switch matrices of a field-programmable gate array (FPGA). The delay variations are isolated from other components of the programmable logic, e.g., look-up tables (LUTs), flip-flops (FFs), etc., using a feature of Xilinx FPGAs called dynamic partial reconfiguration (DPR). A set of partial designs is created to fix the placement of a time-to-digital converter (TDC) and supporting infrastructure to enable the path delays through the target interconnect and switch matrices to be extracted by subtracting out common-mode delay components. Delay variations are analyzed in the different levels of routing resources available within FPGAs, i.e., local routing and across-chip routing. Data are collected from a set of Xilinx Zynq 7010 devices, and a statistical analysis of within-die variations in delay through a set of the randomly-generated and hand-crafted interconnects is presented.

97 MATHEMATICS AND COMPUTING↗

DOE OSTI2026

Maximizing dynamic range and performance of anatase TiO 2 ECRAM through structure and programming

Here, in this study, we investigate the structure-dependent modulation characteristics of all-solid-state three-terminal electrochemical random-access memory (ECRAM) based on an anatase Li x TiO 2 channel. By directly comparing “asymmetric” and “symmetric” ECRAM device architectures, we reveal significant insight into the impact of a non-zero gate-drain open-circuit voltage and its influence on voltage vs. current-controlled gating. We also explore the impact of potentiation/depression write parameters on the symmetry, linearity, and dynamic range of the device response. Together, initial results from optimizing structure and programming approaches yielded unprecedented G max /G min ratios of >1,000 for ECRAM and hundreds of tunable memory states with excellent linearity and symmetry. Simulations based on these ECRAM devices further illustrate the promise of this analog memory technology, achieving near 2% classification error in the MNIST digit recognition benchmark for a range of training parameters compared to a theoretical best of 1.66% and outperforming other device models extracted from the literature.

AIHWKit↗