Engineering Papers⌕ Search

SEARCH · Engineering Papers

Results for “ASIC Design”

Search indexed NASA NTRS and DOE OSTI research on propulsion, heat transfer, battery materials and energy systems. Follow report and document links to the original sources.

Quote a phrase for an exact phrase match. Source license links do not imply unrestricted reuse.

At least 181 records · Page 10
All sourcesNASA NTRSDOE OSTI
DOE OSTI2025

A Radiation-Hard 8-Channel 15-Bit 40-MSPS ADC for the ATLAS Liquid Argon Calorimeter Readout

The custom design of a radiation-hardened, 8-channel, 40-MSPS, 15-bit resolution, 14.2-bit dynamic range, 11.4-ENOB ADC data acquisition ASIC fabricated in a commercial 65-nm triple-well CMOS technology is presented. The ADC is developed for and integrates seamlessly into the readout system for the ATLAS liquid argon (LAr) calorimeter in the high-luminosity large hadron collider (HLLHC) upgrade at CERN, which will require a total of 364 936 ADC channels. A three-stage MDAC+SAR pipelined ADC architecture was designed to meet the physics requirements and scientific goals of the ATLAS experiment. The ADC is a fully self-contained data acquisition system that includes foreground calibration, digital data processing, digital control, and supporting circuitry. The measured performance shows the ADC achieves a competitive dynamic range and SNDR, and it meets or exceeds the ATLAS analog requirements. Radiation tolerance and scalability design considerations were implemented at the device-, circuit-, and system-level. Radiation-hardening-by-design techniques used include redundancy for digital circuits, the use of MiM capacitors, and a hybrid RC-DAC for the ADC core. The ADC ASIC was demonstrated to be robust against the effects of the intense radiation expected in the HL-LHC experimental environment.

DAQ↗
NASA NTRS2004

New Generation Power System for Space Applications

The Deep Space Avionics (DSA) Project is developing a new generation of power system building blocks. Using application specific integrated circuits (ASICs) and power switching modules a scalable power system can be constructed for use on multiple deep space missions including future missions to Mars, comets, Jupiter and its moons. The key developments of the DSA power system effort are five power ASICs and a mod ule for power switching. These components enable a modular and scalab le design approach, which can result in a wide variety of power syste m architectures to meet diverse mission requirements and environments . Each component is radiation hardened to one megarad) total dose. The power switching module can be used for power distribution to regular spacecraft loads, to propulsion valves and actuation of pyrotechnic devices. The number of switching elements per load, pyrotechnic firin gs and valve drivers can be scaled depending on mission needs. Teleme try data is available from the switch module via an I2C data bus. The DSA power system components enable power management and distribution for a variety of power buses and power system architectures employing different types of energy storage and power sources. This paper will describe each power ASIC#s key performance characteristics as well a s recent prototype test results. The power switching module test results will be discussed and will demonstrate its versatility as a multip urpose switch. Finally, the combination of these components will illu strate some of the possible power system architectures achievable fro m small single string systems to large fully redundant systems.

power switching↗
DOE OSTI2023

Pulse shape measurements for neutron/gamma discrimination using the TOFPET2 ASIC

Many highly pixelated organic scintillator detection systems would benefit from independent readout of each scintillator pixel. Recent advances in Silicon Photomultiplier (SiPM) technology makes this goal feasible, however the data acquisition from potentially hundreds or thousands of channels requires a low-cost and compact solution. For pixelated neutron detection with organic scintillators, the capability to distinguish between neutron and gamma interactions using Pulse Shape Discrimination (PSD) is required along with pulse charge and time of arrival. The TOFPET2 ASIC from PETsys Electronics is a 64-channel readout chip providing pulse time and charge integration measurements from SiPMs, and is specifically designed for time-of-flight positron-emission tomography. Using an 8 × 8 array of 6 mm × 6 mm J-series SiPMs from SensL/OnSemi (ArrayJ-60035-64P-PCB), we have studied the energy and PSD performance of the TOFPET2 ASIC using a 4 × 4 array of 6 mm × 6 mm × 30 mm trans -Stilbene crystals from Inrad Optics and a custom SiPM routing board from PETsys Electronics. In conclusion, using a time-over-threshold method, we measure a maximum PSD figure-of-merit of approximately 1.2 at 478 keV (the Compton edge of 662 keV) for a J-series SiPM operating at an over-voltage of 3V.

47 OTHER INSTRUMENTATION↗
NASA NTRS1993

Wide-bandwidth high-resolution search for extraterrestrial intelligence

A third antenna was added to the system. It is a terrestrial low-gain feed, to act as a veto for local interference. The 3-chip design for a 4 megapoint complex FFT was reduced to finished working hardware. The 4-Megachannel circuit board contains 36 MByte of DRAM, 5 CPLDs, the three large FFT ASICs, and 74 ICs in all. The Austek FDP-based Spectrometer/Power Accumulator (SPA) has now been implemented as a 4-layer printed circuit. A PC interface board has been designed and together with its associated user interface and control software allows an IBM compatible computer to control the SPA board, and facilitates the transfer of spectra to the PC for display, processing, and storage. The Feature Recognizer Array cards receive the stream of modulus words from the 4M FFT cards, and forward a greatly thinned set of reports to the PC's in whose backplane they reside. In particular, a powerful ROM-based state-machine architecture has been adopted, and DRAM has been added to permit integration modes when tracking or reobserving source candidates. The general purpose (GP) array consists of twenty '486 PC class computers, each of which receives and processes the data from a feature extractor/correlator board set. The array performs a first analysis on the provided 'features' and then passes this information on to the workstation. The core workstation software is now written. That is, the communication channels between the user interface, the backend monitor program and the PC's have working software.

Horowitz, Paul↗
DOE OSTI2019

A data acquisition system for HV-CMOS sensor research and development in the upgrade of ATLAS experiment

In the High Luminosity LHC (HL-LHC) upgrade of ATLAS experiment in 2026, the new inner tracker detector will be installed. As a promising candidate for the outer layer of the inner tracker detector, the High Voltage CMOS (HV-CMOS) pixel sensors are being investigated by the ATLAS collaboration. A Front-End LInk eXchange (FELIX) based Data Acquisition (DAQ) system is developed for the R&D of the HV-CMOS sensors. A FELIX card with PCIe interface in the back-end is used to control, monitor, calibrate and read out the front-end electronics. In the front-end, a Xilinx evaluation board ZC706 works as the interface between the back- end and custom boards with HV-CMOS sensors and the readout ASIC. In conclusion, the DAQ system was successfully deployed for the testbeam experiment at CERN. Design of the DAQ system, the tuning of sensors and testbeam results will be described in details.

72 PHYSICS OF ELEMENTARY PARTICLES AND FIELDS↗
NASA NTRS1991

A reconfigurable multicarrier demodulator architecture

An architecture based on parallel and pipline design approaches has been developed for the Frequency Division Multiple Access/Time Domain Multiplexed (FDMA/TDM) conversion system. The architecture has two main modules namely the transmultiplexer and the demodulator. The transmultiplexer has two pipelined modules. These are the shared multiplexed polyphase filter and the Fast Fourier Transform (FFT). The demodulator consists of carrier, clock, and data recovery modules which are interactive. Progress on the design of the MultiCarrier Demodulator (MCD) using commercially available chips and Application Specific Integrated Circuits (ASIC) and simulation studies using Viewlogic software will be presented at the conference.

Kwatra, S. C.↗
NASA NTRS1994

VLSI technology for smaller, cheaper, faster return link systems

Very Large Scale Integration (VLSI) Application-specific Integrated Circuit (ASIC) technology has enabled substantially smaller, cheaper, and more capable telemetry data systems. However, the rapid growth in available ASIC fabrication densities has far outpaced the application of this technology to telemetry systems. Available densities have grown by well over an order magnitude since NASA's Goddard Space Flight Center (GSFC) first began developing ASIC's for ground telemetry systems in 1985. To take advantage of these higher integration levels, a new generation of ASIC's for return link telemetry processing is under development. These new submicron devices are designed to further reduce the cost and size of NASA return link processing systems while improving performance. This paper describes these highly integrated processing components.

Nanzetta, Kathy↗
DOE OSTI2023

A 32-channels readout ASIC for X-ray spectrometry and tracking in the GAPS experiment

Here this work describes the architecture and the experimental results from the characterization of a 32-channels mixed-signal Application-Specific Integrated Circuit (ASIC) developed for the readout of the lithium-drifted silicon, Si(Li), detectors of the General AntiParticle Spectrometer (GAPS) experiment dedicated to searching for dark matter. The instrument is designed for the identification of antiprotons, antideuterons and antihelium nuclei from cosmic rays during an Antarctic balloon mission scheduled for late 2024. A full custom integrated circuit, named SLIDER32 (32-channels Si-LI DEtector Readout) ASIC, has been produced in a commercial 180 nm CMOS technology. The ASIC is comprised of 32 low-noise analog readout channels featuring dynamic signal compression to comply with the wide input range, an 11-bit SAR ADC and a digital back-end section which is responsible for channel setting and for sending digital information to the data acquisition system (DAQ). The circuit design criteria and the experimental results are discussed in the paper.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2022

Bridging Python to Silicon: The SODA Toolchain

Systems performing scientific computing, data analysis, and machine learning tasks have a growing demand for application-specific accelerators that can provide high computational performance while meeting strict size and power requirements. However, the algorithms and applications that need to be accelerated are evolving at a rate that is incompatible with manual design processes based on hardware description languages. Agile hardware design tools based on compiler techniques can help by quickly producing an application-specific integrated circuit (ASIC) accelerator starting from a high-level algorithmic description. Here, we present the software-defined accelerator (SODA) synthesizer, a modular and open-source hardware compiler that provides automated end-to-end synthesis from high-level software frameworks to ASIC implementation, relying on multilevel representations to progressively lower and optimize the input code. Our approach does not require the application developer to write any register-transfer level code, and it is able to reach up to 364 giga floating point operations per second (GFLOPS)/W efficiency (32-bit precision) on typical convolutional neural network operators.

97 MATHEMATICS AND COMPUTING↗
NASA NTRS2018

A Novel 3D DRAM Memory Cube Architecture for Space Applications

The first mainstream products in 3D IC design are memory devices where multiple memory tiers are horizontally integrated to offer manifold improvements compared with their 2D counterparts. Unfortunately, none of these existing 3D memory cubes are ready for harsh space environments. This paper presents a new memory cube architecture for space, based on vertical integration of Commercial Off-The-Shelf (COTS), 3D stacked, DRAM memory devices with a custom Radiation-Hardened-By-Design (RHBD) controller offering high memory capacity, robust reliability and low latency.Validation and evaluation of the ASIC controller will be conducted prior to tape-out on a custom FPGA-based emulator platform integrating the 3D-stack.

Yang-Scharlotta, Jean↗
NASA NTRS2016

Detector Control and Data Acquisition for the Wide-Field Infrared Survey Telescope (WFIRST) with a Custom ASIC

The Wide-Field Infrared Survey Telescope (WFIRST) will have the largest near-IR focal plane ever flown by NASA, a total of 18 4K x 4K devices. The project has adopted a system-level approach to detector control and data acquisition where 1) control and processing intelligence is pushed into components closer to the detector to maximize signal integrity, 2) functions are performed at the highest allowable temperatures, and 3) the electronics are designed to ensure that the intrinsic detector noise is the limiting factor for system performance. For WFIRST, the detector arrays operate at 90 to 100 K, the detector control and data acquisition functions are performed by a custom ASIC at 150 to 180 K, and the main data processing electronics are at the ambient temperature of the spacecraft, notionally approx.300 K. The new ASIC is the main interface between the cryogenic detectors and the warm instrument electronics. Its single-chip design provides basic clocking for most types of hybrid detectors with CMOS ROICs. It includes a flexible but simple-to-program sequencer, with the option of microprocessor control for more elaborate readout schemes that may be data-dependent. All analog biases, digital clocks, and analog-to-digital conversion functions are incorporated and are connected to the nearby detectors with a short cable that can provide thermal isolation. The interface to the warm electronics is simple and robust through multiple LVDS channels. It also includes features that support parallel operation of multiple ASICs to control detectors that may have more capability or requirements than can be supported by a single chip.

data acquisition↗
DOE OSTI2025

PSEC5 Physical Verification

Ultra-Fast timing detectors, having a time resolution of 10pSec or less, are becoming increasingly important for many scientific disciplines, including High Energy Physics, Nuclear Physics, Medical Imaging and more. When developing ultra-fast detectors such as MCPs, LAPPDs, LGADs, SNSPDs, it is necessary to have access to a readout system that is low power, can support many channels and is cost effective. The PSEC5 chip was an application specific integrated circuit (ASIC) developed by the pioneering group of Prof. Henry Frisch at University of Chicago and micro electronic engineers at Fermi National Accelerator Laboratory. Three boards were designed, two to implement the readout system for an LAPPD and one to only characterize the PSEC1 chip. The main goal of the project shifted to setting up a testing environment to focus on the characterization of the chip. My student and I tested and characterized this ASIC using the third chip-on-board printed circuit board. Results show the successful fabrication and operation of some of the key building blocks and lead to the suggestions on modification for the second iteration of the chip.

Rico Aniles, H. D. [Unlisted]↗
DOE OSTI2020

Performance of 8 × 8 × 32 and 10 × 10 × 32 mm 3 CdZnTe position-sensitive virtual Frisch-grid detectors for high-energy gamma ray cameras

CdZnTe (CZT) crystals with thicknesses up to 20 mm and diameters up to 75 mm have become available from Redlen Technologies, Inc. for making large-volume gamma-ray detectors. The modified growth and optimized annealing conditions allowed Redlen to minimize the dark current and improve the uniformity of CZT crystals. Two detector designs, pixelated (H3D) and position-sensitive virtual Frisch-grid (VFG), have greatly benefitted from the availability of such big crystals. Encouraging results from testing of 40×40×15 mm 3 pixelated detectors were recently reported by the University of Michigan. In this work, we evaluated the spectroscopic properties of 8×8×32 and 10×10×32 mm 3 crystals configured as position-sensitive VFG detectors. Both digitized waveforms and an analog ASIC were used to read and process the signals from the detectors and test their spectral- and spatial-resolution. The VFG design provides the flexibility to scale-up the dimensions of the detectors for the desired efficiency, while the position information allows for correcting the detectors' response non-uniformity caused by crystal defects and devices geometry, thereby reducing the instrument cost and making them more feasible for emerging applications in gamma-ray astronomy, nonproliferation, portal screening and nuclear safeguards, where large detector arrays are often required.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗
DOE OSTI2025

GRAPH — an readout ASIC for large MCP based detectors

We present a programmable 16 channel, mixed signal, low power readout ASIC, having the project historically named Gigasample Recorder of Analog waveforms from a PHotodetector (GRAPH). It is designed to read large aperture single photon imaging detectors using micro channel plates for charge multiplication, and measuring the detector's response on crossed strips anodes to extrapolate the incoming photon position. Each channel consists of a fast, low power and low noise charge sensitive amplifier, which provides a myriad of coarse and fine programmable options for gain and shaping settings. Further, the amplified signal is recorded using, to our knowledge novel, the Hybrid Universal sampLing Architecture (HULA) ADC. A kind of mixed signal double buffer memory, that enables concurrent waveform recording, and selected event digitized data extraction. The sampling frequency is freely adjustable between few kHz up to 125 MHz, while the chip's internal digital memory holds a history 2048 samples for each channel, with a digital headroom of 12 bits. An optimized region of interest sample-read algorithm allows to extract the information just around the event pulse peak, while selecting the next event, thus substantially reducing the operational dead time. The chip is designed in 130 nm TSMC CMOS technology, and its power consumption is around 47 mW per channel.

47 OTHER INSTRUMENTATION↗
DOE OSTI2026

Estimating Residual Gas Beam Loss in the BNL AGS Booster:Model, Numerical Tools, and Implications for a Polarimeter Chamber

Beamloss from residual gas scattering is calculated for a storage ring of circumference C = 200m, covering a linear magnetic rigidity ramp from B ρ inj = 1.25Tm to B ρ ext = 9.50Tm over tramp = 1.00s. Three loss mechanisms are considered: nuclear inelastic reactions, single Coulomb scattering beyond the acceptance angle of the machine, and charge-state exchange for heavy ions. Calculations are performed for protons and Au 32+ ions, the latter being the charge state delivered by the EBIS pre-injector into the BNL AGS Booster. At a baseline vacuum of P 0 = 5 × 10 −11 mbar the integrated fractional beam loss over the full ramp is negligible for protons (< 0.001%) and 33.1% for Au 32+ . The impact of a 1m polarimeter section at elevated pressure P s = 5 × 10 −9 mbar is evaluated: the proton loss remains negligible, while the Au 32+ loss rises to 45.1%, establishing the vacuum requirement for the polarimeter chamber. In the present compact approximate model, Au 32+ losses are dominated by charge exchange at injection, while proton losses are dominated by single Coulomb scattering. The design, outgassing budget, pumping strategy, and commissioning sequence for a UHV polarimeter chamber housing silicon detectors and ASICs are described in detail.

43 PARTICLE ACCELERATORS↗
DOE OSTI2024

Fail-Safe Logic Design Strategies Within Modern FPGA Architectures

Fail-safe computing refers to computing systems that revert to a non-operational safe state when a fault occurs. In this paper, we investigate a circuit level technique as mitigation for single event upsets (SEUs) and fault injection attacks on field programmable gate arrays (FPGAs), and analyze the effectiveness of the technique as a fail-safe monitor for an encryption algorithm. The propagation of fault effects through FPGA primitives including lookup tables (LUTs) and programmable interconnect points (PIPs) is assessed within an FPGA architecture created using an open source tool, and validated using fault injection experiments on an FPGA. The analysis reveals additional vulnerabilities exist within reconfigurable architectures over those in equivalent fail-safe application specific integrated circuit (ASIC), thus requiring a more elaborate network of redundant circuits and checking logic. The configuration memory bits (CMBs), which configure routing and designate logic functions within the LUTs of the FPGA, add complexity to fail-safe design strategies by introducing additional fault conditions and fault propagation paths. A resource-efficient fail-safe circuit design technique called DEsign for Fail-safe in reCONfigurable systems (DEFCON) is proposed. The benefits and limitations associated with DEFCON are described in the context of fault injection experiments carried out as simulations and in FPGA hardware.

Bhakta, Priya A. [Univ. of New Mexico, Albuquerque↗
DOE OSTI2020

The CLAS12 Micromegas Vertex Tracker

The Micromegas Vertex Tracker was designed to improve upon the tracking capabilities of the baseline design of the CLAS12 spectrometer in Hall~B at Jefferson Laboratory. A Barrel Micromegas Tracker made with six concentric cylinders, each made of three 120$^\circ$-sector tiles, surrounds the Silicon Vertex Tracker, and a Forward Micromegas Tracker composed of 6 disks is placed 30~cm downstream of the liquid-hydrogen target. Both trackers sit in a 5~T solenoid magnetic field. All Micromegas elements are based on resistive technology to withstand luminosities up to $10^{35}$~cm$^{-2}$s$^{-1}$, as well as on bulk technology to enforce gain uniformity and mechanical robustness. Due to the high magnetic field, dedicated electronics have been designed and displaced $\sim$2~m away from the detectors. The electronics readout is based on the DREAM ASICs that allow sustained operation up to 20~kHz trigger rate at the maximum luminosity.

46 INSTRUMENTATION RELATED TO NUCLEAR SCIENCE AND ↗