LGAD-in-CMOS Design Studies

Abstract

We describe a process flow for a CMOS sensor with intrinsic gain. The design is based on a base wafer which is prepared with closely spaced buried n and p doping layers that form an amplifying high field gain region when the device is biased. A deep n-well forms the collecting electrode. The buried n layer serves to moderate the internal field so that the CMOS transistors within the n-well remain within their operating region.