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DOE OSTI · 1483256

Multiple-core computer processor for reverse time migration

Shalf, John·Donofrio, David·Oliker, Leonid·Kruger, Jens·Williams, Samuel
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Abstract

A multi-core computer processor including a plurality of processor cores interconnected in a Network-on-Chip (NoC) architecture, a plurality of caches, each of the plurality of caches being associated with one and only one of the plurality of processor cores, and a plurality of memories, each of the plurality of memories being associated with a different set of at least one of the plurality of processor cores and each of the plurality of memories being configured to be visible in a global memory address space such that the plurality of memories are visible to two or more of the plurality of processor cores, wherein at least one of a number of the processor cores, a size of each of the plurality of caches, or a size of each of the plurality of memories is configured for performing a reverse-time-migration (RTM) computation.

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97 MATHEMATICS AND COMPUTING

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BibTeXRIS

Shalf, John, Donofrio, David, Oliker, Leonid, Kruger, Jens, Williams, Samuel. 2018-09-18. Multiple-core computer processor for reverse time migration. https://www.osti.gov/biblio/1483256

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