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DOE OSTI · 1023908

Error correcting code with chip kill capability and power saving enhancement

Gara, Alan G·Chen, Dong·Coteus, Paul W·Flynn, William T·Marcella, James A·Takken, Todd·Trager, Barry M·Winograd, Shmuel
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Abstract

A method and system are disclosed for detecting memory chip failure in a computer memory system. The method comprises the steps of accessing user data from a set of user data chips, and testing the user data for errors using data from a set of system data chips. This testing is done by generating a sequence of check symbols from the user data, grouping the user data into a sequence of data symbols, and computing a specified sequence of syndromes. If all the syndromes are zero, the user data has no errors. If one of the syndromes is non-zero, then a set of discriminator expressions are computed, and used to determine whether a single or double symbol error has occurred. In the preferred embodiment, less than two full system data chips are used for testing and correcting the user data.

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97 MATHEMATICS AND COMPUTING

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Gara, Alan G, Chen, Dong, Coteus, Paul W, Flynn, William T, Marcella, James A, Takken, Todd, Trager, Barry M, Winograd, Shmuel. 2011-08-30. Error correcting code with chip kill capability and power saving enhancement. https://www.osti.gov/biblio/1023908

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