Mixed Voltage VLSI Design

Rennels, D.; Alkalaj, L.; Panwar, R.

NASA NTRS · 20210001270

Mixed Voltage VLSI Design

Abstract

We present a technique for minimizing the power dissipated in a VLSI chip by lowering the operating voltage without any significant penalty in the chip throughput even though low voltage operation results in slower circuits.

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VLSI chip critical path two voltages

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BibTeX RIS

Rennels, D., Alkalaj, L., Panwar, R.. 1993-11-01. Mixed Voltage VLSI Design. https://ntrs.nasa.gov/citations/20210001270

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