A new variable testability measure

Abstract

In this paper, we propose a new Variable Testability Measure (VTM) for implementing testability at the high-level synthesis stage of the design process of integrated circuits. This new approach, based on binary decision diagrams, representing fully functional blocks of a circuit, and on their cyclomatic testability measures. It manipulates dataflow blocks to predict whether the circuit is testable and the vector set required to test it.