NASA NTRS · 19850000456
Multiplier Architecture for Coding Circuits
Abstract
Multipliers based on new algorithm for Galois-field (GF) arithmetic regular and expandable. Pipeline structures used for computing both multiplications and inverses. Designs suitable for implementation in very-large-scale integrated (VLSI) circuits. This general type of inverter and multiplier architecture especially useful in performing finite-field arithmetic of Reed-Solomon error-correcting codes and of some cryptographic algorithms.
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Wang, C. C., Truong, T. K., Shao, H. M., Deutsch, L. J.. 1986-03-01. Multiplier Architecture for Coding Circuits. https://ntrs.nasa.gov/citations/19850000456
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