NASA NTRS · 19780030714
A compact high-speed parallel multiplication scheme
Abstract
This paper discusses a compact, fast, parallel multiplication scheme of the generation-reduction type using generalized Dadda-type pseudoadders for reduction and m x m multipliers for generation. The implications of present and future LSI are considered, a partitioning algorithm is presented, and the results obtained for a 24 x 24-bit implementation are discussed.
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Stenzel, W. J., Kubitz, W. J., Garcia, G. H.. 1977-10-01. A compact high-speed parallel multiplication scheme. https://ntrs.nasa.gov/citations/19780030714
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