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Yu, Kellen [Cornell U.]

Publications and source records attributed to Yu, Kellen [Cornell U.].

Real-Time Inference For MI/RR Deblending

The Fermilab Main Injector (MI) and Recycler Ring (RR) share a common beam loss monitor (BLM) system, making loss events difficult to attribute to their source machine when beam is present in both simultaneously. The Real-time Edge AI for Distributed Systems (READS) project addresses this by deblending BLM readings in real time using machine learning (ML). The current FPGA based implementation meets the sub-3 ms latency requirement but carries a resource intensive hls4ml development cycle, motivating exploration of GPU based deployment. This paper characterizes inference latency on an NVIDIA Jetson Orin Nano and introduces a packet organization scheme for assembling synchronized event frames from seven distributed BLM DAQ streams. Using a Python based DAQ simulation with injected timing jitter in place of unavailable live beam data, the pipeline achieved an average end to end latency of 0.456 ms (σ = 0.122 ms) across 167,000 test frames, comfortably meeting the timing constraint. Early outliers were attributed to TensorRT warm-up rather than steady state limitations, suggesting GPU based inference is a viable alternative to the existing FPGA implementation.

Yu, Kellen [Cornell U.]↗

Short Circuit Detection and Voltage Sense for High Voltage Ionization Tube Power Supplies

Fermilab's PIP-II upgrade requires new rack-mounted power supplies for Beam Loss Monitor (BLM) ionization tubes compatible with the microTCA 4.1 standard, supporting high-side current measurement for short circuit detection, voltage sense telemetry, and low-side current measurement for beam loss readout. This work presents the design and preliminary schematic of such a supply. A resistive current sensing approach was chosen over inductive, optical, and Hall-effect alternatives for its independence from cable length and component availability. A 500 mΩ inline shunt steps the 2 kV common mode voltage down to roughly 70 V, producing a ~27 μV pulse during a short, which is amplified 500x, compared against a 14-bit DAC threshold, and latched to drive a fault line. Voltage sense steps the 2 kV output down at a 1V/1000V ratio, buffers it with a low bias current amplifier, and digitizes it via a 24-bit ADC over SPI. Onboard power is regulated from 12 V down to isolated 5 V and 3.3 V rails, with capacitive isolation on FPGA communication lines. Lumped parameter models were developed for the ionization tube (0.327 nF, 20 to 200 GΩ dynamic resistance) and the RG-58 coaxial cable to support the design. Component selection is complete and a preliminary schematic has been drawn in Altium Designer, forming the foundation for future prototyping and validation.

Yu, Kellen [Cornell U.]↗