Engineering topics
Publications and source records attributed to Yang-Scharlotta, Jean.
We present single event effects (SEE) evaluation of the Everspin Technologies 1Gb non-volatile ST-DDR4 spin-transfer torque MRAM.
The purpose of the study presented in this paper is to extend the test period of a selected set of electronics parts at cryogenic condition to dwell period of about 24 hours to demonstrate extreme cold operational capability of these components. The parts tested are tantalum polymer, BX and P90 type ceramic capacitors, thick film resistors, analog multiplexers, a digital inverter, and a D-flip-flop. These parts were tested to assist identifying candidate components that can be used for development of a cold capable telemetry board. There are several past investigations that have shown that COTS (commercial-off-the-shelf) capacitors and resistors tested at cryogenic temperatures and frequencies up to 10MHz did not exhibit significant changes in capacitance and resistance values. Also, there are several test results for active parts. These past tests collected measurements during a temperature sweep from room temperature down to cryogenic temperature with very short dwell time at cryogenic temperature, and back to room temperature. This study extends the operational dwell time to at least 24 hours and returning to room temperature operation without significant degradation in performance, thus, demonstrating the potential for longer dwell time in actual operation in these extreme cold temperatures and a method for identifying the cold operability.
The first mainstream products in 3D IC design are memory devices where multiple memory tiers are horizontally integrated to offer manifold improvements compared with their 2D counterparts. Unfortunately, none of these existing 3D memory cubes are ready for harsh space environments. This paper presents a new memory cube architecture for space, based on vertical integration of Commercial Off-The-Shelf (COTS), 3D stacked, DRAM memory devices with a custom Radiation-Hardened-By-Design (RHBD) controller offering high memory capacity, robust reliability and low latency.Validation and evaluation of the ASIC controller will be conducted prior to tape-out on a custom FPGA-based emulator platform integrating the 3D-stack.
MRAM and DRAM memory technologies identified for possible radiation hardening were investigated for memory-array- and controller-level radiation sensitivity. TID and SEE performance of memory arrays and associated cells is good, but with some questions about viability of hardening of problematic control circuitry. Control-circuitry-related SEE problems are highlighted. TID data are focused on memory arrays only.
Memory technologies were reviewed for radiation effects performance in order to determine the most cost-efficient target for a possible memory investment targeted at creating a memory component of general applicability for space use. TID and SEL trends that had indicated improvement in intrinsic performance based on scaling cannot be trusted. SEE hardening of memory arrays is prohibitive in terms of cell-level power and area requirements. Radiation-hardened cells and custom controllers are recommended for future memory developments.
Independent and coupled effects of radiation and endurance on commercial NAND Flash memory is studied using pulsed programming enabled by interrupting the programming command at the chip-level. The effects of total ionization dose (TID) and endurance stress increase and decrease, respectively, the number of pulses needed to program an entire page. The coupled effect of endurance stress and TID appear to exhibit linear correlation. A neutral electron/ hole trap model is evaluated and correlates well with our results.
We present reliability data combined with total dose gamma radiation for one of the first commercially available resistive memory devices. These Tantalum Oxide (TaOX)-based resistive memory chips demonstrate operation in dynamic program and erase testing up to ~130 Krad(Si) of 60Co gamma dose. In static and unbiased conditions, the stored data in the memory cells were able to withstand up to 50Mrad(Si) of exposure. The access circuitry, though, seemed less robust to gamma radiation and was able to operate only up to a total dose of 3Mrad(Si). Post exposure reliability as indicated by endurance, cycling error rate, and data retention tests showed no detectable impact from the combination with prior gamma irradiation. Overall, the total dose radiation tolerance of the commercial TaOx-based resistive memory chip appears to be higher than flash memory chips and in agreement with prior tests conducted with single cell resistive memories.
No abstract available